Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-11
2007-09-11
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C257S773000
Reexamination Certificate
active
10991360
ABSTRACT:
Enlarged spacing is provided between rows of vias in a ball grid array (BGA) multilayered printed wiring board land pattern in which the lands in the pattern are connected to the vias by a link connector by rotating, elongating, and/or truncating selected consecutive link connectors and rotating their respective corresponding vias in a row or column or selected consecutive rows or columns to achieve the enlarged spacing between rows or columns of vias in the BGA land pattern. Enhanced spacing between selected grid columns or rows of vias is provided such that some of the grid pitches for the vias are equal to that of the standard BGA and at least some are of a greater grid pitch.
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Alcatel
Garbowski Leigh M.
Zegeer Jim
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