Off-diameter method for preparing semiconductor wafers

Abrading – Abrading process – Glass or stone abrading

Reexamination Certificate

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C451S011000, C451S209000

Reexamination Certificate

active

06461224

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor fabrication and, more particularly, to methods for preparing semiconductor wafers in which preparation operations are performed on a vertically oriented wafer. The preparation is configured to take place in a single enclosure apparatus.
In the fabrication of semiconductor devices, a variety of wafer preparation operations are performed. By way of example, these wafer preparation operations include cleaning operations and polishing/planarization operations, e.g., chemical mechanical planarization (CMP). One known polishing/planarization technique uses platens with planetary polishing motion. One disadvantage of this technique is that it requires multi-step procedures, which are time-consuming and relatively expensive. Another disadvantage of this technique is that it tends to produce wafers having surfaces that suffer from a relatively high degree of topographic variations.
Another known polishing/planarization technique involves circumferential polishing. In one known circumferential polishing system, a wafer is rotated in a vertical orientation by wafer drive rollers. As the wafer is rotated, a pair of cylindrical polishing pads is brought into contact with the opposing surfaces of the wafer. The polishing pads are mounted on counter-rotating mandrels disposed on opposite sides of the wafer being processed. The mandrels span across the diameter of the wafer so as to pass over the wafer center. The rotation of the mandrels causes a rotary pad motion perpendicular to the wafer diameter in a circumferential direction. During the polishing operation, nozzles direct sprays of liquid, e.g., an abrasive slurry, a chemical solution, or a rinse solution, on the opposing surfaces of the wafer.
One drawback of this known circumferential polishing system is that it provides only circumferential polishing motion. As such, the relative velocity of each pad is not uniform across each wafer surface, with the velocity near the wafer edge being greater than the velocity near the wafer center. This is problematic because it not only results in the creation of circumferential residual scratches on each of wafer surfaces, but also results in a more wafer material being removed from the center portion of the wafer than near the perimeter due to the greater dwell time experienced by the center portion of the wafer. As a consequence of this nonuniform material removal rate, each of the opposing surfaces of the wafer tends to have a flared contour, i.e., a contour in which the central portion is depressed relative to the edge portions. As the semiconductor industry moves toward the use of smaller, e.g., 0.18 &mgr;m and smaller, feature sizes, such flared contours are undesirable.
In view of the foregoing, there is a need for a method and apparatus for circumferential wafer preparation that minimizes the creation of circumferential residual scratches, provides processed wafers have desired surface contours, and enables multiple wafer preparation operations to be performed on a wafer without moving the wafer between stations.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills this need by providing methods for preparing wafers.
In accordance with one aspect of the present invention, a method for preparing a semiconductor wafer is disclosed. The method includes rotating a semiconductor wafer in a vertical orientation, and the wafer having first and second opposing surfaces. The method further includes contacting each of the first and second opposing surfaces of the wafer with a cylindrical wafer preparation member so as to define a substantially linear contact area. The cylindrical wafer preparation members are disposed in an opposing relationship such that the contact areas are defined at corresponding locations on the first and second opposing surfaces. Then, the method includes controlling at least one wafer preparation parameter to obtain a variable wafer material removal rate as the contact areas defined on the first and second opposing surfaces are moved from a first position to a second position. The variable wafer material removal rate being formulated to provide the wafer with a substantially uniform thickness.
In accordance with another aspect of the present invention, a method for polishing a semiconductor wafer is provided. The method includes rotating a semiconductor wafer in a vertical orientation, the wafer having first and second opposing surfaces. The first and second opposing surfaces of the wafer are then contacted with a cylindrical polishing pad so as to define a substantially linear contact area. The cylindrical polishing pads being disposed in an opposing relationship such that the contact areas are defined at corresponding locations on the first and second opposing surfaces. The method then includes controlling at least one wafer preparation parameter to obtain a variable wafer material removal rate as the contact areas defined on the first and second opposing surfaces are moved from a first position to a second position. The variable wafer material removal rate being formulated to provide the wafer with a substantially uniform thickness.
In yet another aspect of the invention, a method for polishing a semiconductor wafer is disclosed. The method includes rotating a semiconductor wafer in a vertical orientation, the wafer having first and second opposing surfaces. Then, the method proceeds to contacting each of the first and second opposing surfaces of the wafer with a cylindrical polishing pad so as to define a substantially linear contact area. The cylindrical polishing pads are counter-rotated and are disposed in an opposing relationship such that the contact areas are defined at corresponding locations on the first and second opposing surfaces. A rate at which the wafer is moved in a vertical direction is controlled to move the contact areas defined on the first and second opposing surfaces from a first position to a second position. The rate at which the wafer is moved in the vertical direction is formulated to provide the wafer with a substantially uniform thickness.
The advantages of the present invention are many and substantial. Most notably, the wafer positioned so as to prepare the desired surface location of the wafer. This ability provides powerful control over the preparation process and enables desired amounts of material to be removed from just the right region of a wafer.
It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


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patent: WO 99/40611 (1999-08-01), None

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