Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1995-11-01
1998-03-10
Santamauro, Jon
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 86, 326 87, H03K 190185, H03K 190948
Patent
active
057265895
ABSTRACT:
An output driver circuit for a semiconductor chip has a push-pull output with a P-channel pull-up and an N-channel pull-down. Predrivers produce push-pull outputs for driving the gates of the output driver. In previous circuits, a stacked arrangement was usually employed where the N-channel pull-down transistor had another N-channel transistor, with gate connected to the voltage supply, in series with it. In this invention, a parallel N-channel or P-channel transistor is employed to shunt part of the current at the beginning of a transition from high-to-low at the output node of the off-chip driver circuit, and thus lower the voltage across the pull-down transistor to a level which will avoid hot-electron degradation. This parallel transistor is small compared to the main N-channel pull-down, and serves to reduce the output node voltage to a level which does not present a likelihood of hot-electron effects in the main pull-down device. Thus, large current flow through the N-channel pull-down is delayed until the voltage is reduced to an acceptable level. At the same time, this delay is not such as would unduly compromise the high speed nature of the circuits.
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Cahill Joseph J.
Williams Robert R.
International Business Machines - Corporation
Santamauro Jon
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