Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Patent
1993-05-05
1995-01-24
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
257692, 257666, H01L 2348, H01L 2944, H01L 2952, H01L 2960
Patent
active
053844874
ABSTRACT:
A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads. Constraining the location of the power-carrying bond pads to an interior area of the die approximately one half of the die area, and substantially centered about the axis, keeps longitudinal thermal displacements of the ends of leadframe fingers or bond wires connected to the power-carrying bond pads relatively small compared to those experienced in peripheral bond pad placement (at the die edges), and ensures shorter, more direct internal paths to circuitry on the die.
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Pasch Nicholas F.
Rostoker Michael D.
Zelayeta Joe
Clark S. V.
James Andrew J.
LSI Logic Corporation
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