NVRAM array architecture utilizing common bitline and wordline

Static information storage and retrieval – Floating gate – Particular connection

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36518505, 36518511, G11C 1400

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active

060210664

ABSTRACT:
A non-volatile random access memory (NVRAM) array and chip architecture. An NVRAM array formed of at least two sub-arrays of pairs of NVRAM cells, each including three FETs stacked in a NAND-like structure. Each pair shares a bit line and a word line and each cell has a separate control gate and source gate from the other cell of the pair. For each sub-array, one cell in each pair us connected to a first control gate and source gate and the other cell in each pair is connected to another control gate and source gate. After sequentially accessing part or all of the cells on one source gate or one control gate in one sub-array, sequential access continues in another sub-array before accessing cells on the other source gate or control gate in the other sub-array. Selecting cells in one sub-array (i.e. driving a source gate or control gate) occurs as previously selected cells in another sub-array are accessed.

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