Numerically-controlled phase-lock loop with input timing...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S354000, C375S371000, C375S375000, C455S260000, C455S516000, C327S141000, C327S147000, C327S156000

Reexamination Certificate

active

07746972

ABSTRACT:
A numerically-controlled phase-lock loop with input clock dependent ratio adjustment provides for narrower-bandwidth loops that lock to a wide range of frequencies and/or operation with an absent or degraded input timing reference. A timing reference characteristic detector determines an input frequency range of the input timing reference signal, the data type of the timing reference, and/or whether a timing reference signal of sufficient quality is present. A numerically controlled oscillator is controlled by a numeric ratio that is adjusted to provide the desired clock frequency output in conformity with the detected frequency range and/or data type. If the timing reference signal is absent or degraded, then the numeric ratio can be set to a fixed value or a local timing reference can be applied in order to generate the desired clock output frequency.

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