Electronic digital logic circuitry – Threshold
Reexamination Certificate
2005-05-31
2005-05-31
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Threshold
C326S093000, C326S121000
Reexamination Certificate
active
06900658
ABSTRACT:
A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.
REFERENCES:
patent: 3715603 (1973-02-01), Lerch
patent: 4542525 (1985-09-01), Hopf
patent: 4845633 (1989-07-01), Furtek
patent: 5053645 (1991-10-01), Harada
patent: 5121003 (1992-06-01), Williams
patent: 5305463 (1994-04-01), Fant et al.
patent: 5382844 (1995-01-01), Knauer
patent: 5386424 (1995-01-01), Driscoll et al.
patent: 5434520 (1995-07-01), Yetter et al.
patent: 5640105 (1997-06-01), Sobelman et al.
patent: 5656948 (1997-08-01), Sobelman et al.
M.R. Greenstreet, T.E. Williams, and J. Staunstrup, Self-Timed Iteration, Elsevier Science Publishers B.V. (North-Holland), IFIP, 1988, pp. 309-322.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt, Automatic Synthesis of Asynchronous Circuits from High-Level Specifications, IEEE Transactions on Computer-Aided Design, vol. 8, No. 11, Nov. 1989, pp. 1185-1205.
Ted Williams, Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
Jens Sparso and Jorgen Staunstrup, Delay-insensitive multi-ring structures, Integration, the VLSI Journal 15, 1993, Elsevier Science Publishers B.V., pp. 313-340.
Tzyh-Yung Wuu and Sarma B.K. Vrudhula, A Design of a Fast and Area Efficient Multi-Input Muller C-element, IEEE Transactions on VLSI Systems, vol. 1, No. 2, Jun. 1993, pp. 215-219.
Marc Renaudin and Bachar El Hassan, The Design of Fast Asynchronous Adder Structures and Their Implementation Using D.C.V.S. Logic, Int'l. Symposium on Circuits & Systems, vol. 4, 1994, pp. 291-294.
Richard G. Burford, Xingcha Fan and Neil W. Bergmann, An 180 Mhz 16 bit Multiplier Using Asynchronous Logic Design Techniques, IEEE 1994 Custom Integrated Circuits Conference, pp. 215-218.
Ted Williams, Self-Timed Rings and Their Application to Division, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
Fant Karl M.
Sobelman Gerald E.
Tan Vibol
Theseus Logic Inc.
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