Null convention register file

Electronic digital logic circuitry – Multifunctional or programmable – Array

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39580025, 326 56, 326 59, 711104, 365168, G06F 1582

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active

058965416

ABSTRACT:
A NULL convention logic bus includes: a plurality of bus transmission lines; a plurality of NULL convention transmitter ports; and a plurality of NULL convention receiver ports. Each NULL convention transmitter port propagates alternating wavefronts of data an NULL across the bus transmission lines to a NULL convention receiver port. A pipeline bus includes NULL convention storage registers at the transmitter ports. A FIFO pipeline bus includes NULL convention storage registers at the receiver ports. A NULL convention register file includes: a NULL convention input register; and a plurality of NULL convention storage registers. The input register synchronously propagates alternating wavefronts of NULL and data to an addressed NULL convention storage register.

REFERENCES:
patent: 5777709 (1998-07-01), Xu
M.R. Greenstreet, T.E. Williams, and J. Staunstrup, Self-Timed Iteration, Elsevier Science Publishers B.V. (North-Holland), IFIP, 1988, pp. 309-322.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt, Automatic Synthesis of Asynchronous Circuits from High-Level Specifications, IEEE Transactions on Computer-Aided Design, vol. 8, No. 11, Nov. 1989, pp. 1185-1205.
Ted Williams, Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
Jens Sparso and Jorgen Staunstrup, Delay-insensitive multi-ring structures, Integration, the VLSI Journal 15, 1993, Elsevier Science Publishers B.V., pp. 313-340.
Tzyh-Yung Wuu and Sarma B.K. Vrudhula, A Design of a Fast and Area Efficient Multi-Input Muller C-element, IEEE Transactions on VLSI Systems, vol. 1, No. 2, Jun. 1993, pp. 215-219.
Marc Renaudin and Bachar El Hassan, The Design of Fast Asynchronous Adder Structures and Their Implementation Using D.C.V.S. Logic, Int'l. Symposium on Circuits & Systems, vol. 4, 1994, pp. 291-294.
Richard G. Burford, Xingcha Fan and Neil W. Bergmann, An 180 Mhz 16 bit Multiplier Using Asynchronous Logic Design Techniques, IEEE 1994 Custom Integrated Circuits Conference, pp. 215-218.
Ted Williams, Self-Timed Rings and Their Application to Division, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
David E. Muller, Asynchronous Logics and Application to Information Processing, Stanford University Press, Switching Theory In Space Technology, pp. 289-297, 1963.
Narinder Pal Singh, A Design Methodology For Self-Timed Systems, Massachusetts Institute of Technology, MIT/LCS/TR-258, Feb. 1981.
T.S. Anatharaman, A Delay Insensitive Regular Expression Recognizer, Dept. of Computer Science, Carnegie-Mellon University, CMU-CS-89-109, Jan. 1989.
Jens Sparso, et al., Design of Delay Insensitive Circuits Using Multi-Ring Structures, European Design Automation Conference, IEEE 0-8186-2780, pp. 15-20, Aug. 1992.
Lawrence G. Heller, et al., Cascode Voltage Switch Logic: A Different CMOS Logic Family, ISSCC 84 Digest of Technical Papers, IEEE, pp. 16-17, Feb. 1984.
Lars S. Nielsen and Jens Sparso, A Low-Power Asynchronous Data-Path For a FIR Filter Bank, IEEE 0-8186-7298-6/96, pp. 197-207, Jun. 1996.
Stephen H. Unger, Asynchronous Sequential Switching Circuits, 1969, pp. 221-229.
Carver Mead & Lyn Conway, Introduction to VLSI Systems, 1980, pp. 242-262.
Ivan E. Sutherland, Micropipelines, Communications of the ACM, Dec. 1989, vol. 32, No. 6.
Tadashi Shibata & Tadahiro Ohmi, A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, IEEE Transactions On Electron Devices, Dec. 1992, vol. 39, No. 6, pp. 1444-1455.
Anthony S. Wojcik & Kwang-Ya Fang, On The Design Of Three-Valued Asynchronous Modules, IEEE Transactions On Computers, Oct. 1980, vol. C-29, No. 10, pp. 889-989.
Mark Edward Dean, Strip: A Self-Time Risc Processor, Stanford University Computer Systems Laboratory Technical Report No. CSL-TR-92-543, Stanford, CA, Jul. 1992.
Daniel Hampel & Robert Winder, Threshold Logic, IEEE Spectrum, May 1971, pp. 32-39.
Janusz A. Brzozowski & Carl-Johan H. Seger, Asynchronous Circuits--Monographs in Computer Science, Springer-Verlag New York, Inc., 1995, New York, NY.
Brunvand, "The NSP Processor," IEEE, 1993, pp. 428-435.
Patel et al., "Evaluation of Self-Timed Systems for VLSI," Electronics Letters, Feb. 1989, pp. 215-217.

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