Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-02-14
2006-02-14
Smith, Matthew (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06998675
ABSTRACT:
The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain size on a tunnel dielectric layer. Nucleation sites are formed by exposing the tunnel dielectric layer to a first set of conditions including a first temperature and a first atmosphere selected to optimize nucleation site size and distribution density across the tunnel dielectric layer. A polycrystalline floating gate layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of conditions including a second temperature and a second atmosphere selected to optimize polycrystalline grain size and distribution density across the polycrystalline floating gate layer.
REFERENCES:
patent: 4742020 (1988-05-01), Roy
patent: 5102832 (1992-04-01), Tuttle
patent: 5112773 (1992-05-01), Tuttle
patent: 5320880 (1994-06-01), Sandhu et al.
patent: 5340765 (1994-08-01), Dennison et al.
patent: 5366917 (1994-11-01), Watanabe et al.
patent: 5385863 (1995-01-01), Tatsumi et al.
patent: 5445982 (1995-08-01), Hwang
patent: 5885884 (1999-03-01), Jan et al.
patent: 5888295 (1999-03-01), Sandhu et al.
patent: 5914896 (1999-06-01), Lee et al.
patent: 5943571 (1999-08-01), Schaefer et al.
patent: 5953254 (1999-09-01), Pourkeramati
patent: 6043124 (2000-03-01), Wu
patent: 6090666 (2000-07-01), Ueda et al.
patent: 6194292 (2001-02-01), Tsu et al.
patent: 6287915 (2001-09-01), Muramatsu
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6762451 (2004-07-01), Weimer
patent: 6791141 (2004-09-01), Keller et al.
Sakai, Akira, et al.,Novel seeding method for the growth of polycrystalline Si films with hemispherical grains, Applied Physics Letters, vol. 61, No. 2, Jul. 13, 1992, pp. 159-161.
Watanabe, et al.,Hemispherical Grained Si Formation on in-situ Phosphorus Doped Amorphous-Si Electrode for 256Mb DRAM's Capacitor, IEEE Transactions on Electron Devices, vol. 42, No. 7, Jul. 1995, pp. 1247-1254.
Knobbe Martens Olson & Bear LLP
Malsawma Lex H.
Smith Matthew
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