NROM memory device with enhanced endurance

Details NROM memory device with enhanced endurance NROM memory device with enhanced endurance

2006-10-05

2008-07-15

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185220, C365S185330

Reexamination Certificate

active

07400538

ABSTRACT:
The efficient removal of parasitic electron charges from the ONO structure of an NROM cell by periodically applying a negative gate refresh voltage in a way that injects holes from the substrate into the ONO structure. Initially, after each erase pulse is generated and an unacceptable erase state is detected, the erase pulse magnitude is incrementally increased to compensate for the increasing parasitic electrons. When a predetermined maximum drain voltage is reached, the negative gate refresh voltage is applied to refresh the ONO structure, and the drain voltage is reset to an initial state. A novel NROM cell uses a P+ doped polysilicon gate or Top Oxide produced with a high-k dielectric (Alumina) to facilitate blocking the injection of gate electrons, and the Bottom Oxide thickness is selectively thinned to increase hole injection.

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