NOR type semiconductor memory device and a method for reading da

Details NOR type semiconductor memory device and a method for reading da NOR type semiconductor memory device and a method for reading da

1998-04-13

2000-02-22

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523003, G11C 800

Patent

active

060288132

ABSTRACT:
Disclosed is a semiconductor memory device and a method for reading data stored therein. The device comprises a cell array having a plurality of groups, sub-bit lines, word lines, main bit lines, each of the groups having memory cells connected in parallel between the sub bit lines, first NMOS transistors for selecting even-numbered groups of the groups, second NMOS transistors for selecting odd-numbered groups of the groups, a voltage generating circuit for generating a first voltage by dividing an externally applied power supply voltage, a row selecting circuit for selecting one of the word lines in response to an external row address signal; a column selecting circuit for selecting column of the cell array in response to an external column address signal, and a sense amplifier circuit for sensing the data of memory cell associated with the selected word line and the selected main bit line. The method comprising the steps of precharging the main bit lines to the first voltage; and sensing the data of memory cell associated to the selected word line and the selected main bit line by suppling the first voltage onto the main bit lines and the selected word line, and suppling a second voltage to at least one of the main bit lines adjacent to the selected main bit line in response to the column address signal. A voltage level applied on a selected word line during a data sensing operation is equal to a voltage applied on all the main bit lines during bit line precharge operation. Alternatively, the voltage level applied on the selected word line is lower than the voltage level applied on the main bit lines. Thus, a voltage difference between respective gates and sources of the cells adjacent to the selected memory cell is 0 V, so that all of the cells are turned off during the data sensing period.

REFERENCES:
patent: 5650979 (1997-07-01), Komarek et al.
patent: 5793698 (1998-08-01), Komarek et al.
"16Mb Rom Design Using Bank Select Architecture" M. Okada et al. Integrated Circuits group, Sharp Corporation 2613-1, Ichinomoto, Teni, Nara 632, Japan.

Affiliated with

Also associated with

Rating

NOR type semiconductor memory device and a method for reading da does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with NOR type semiconductor memory device and a method for reading da, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NOR type semiconductor memory device and a method for reading da will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-525965