NOR-type nonvolatile semiconductor memory device and a method fo

Details NOR-type nonvolatile semiconductor memory device and a method fo NOR-type nonvolatile semiconductor memory device and a method fo

1998-12-29

2000-03-28

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36518909, G11C 800

Patent

active

060440333

ABSTRACT:
A NOR-type read only memory with improved read-out performance includes a memory cell array having a plurality of memory cell blocks, each memory block including a plurality of bit lines, a column decoder for generating a plurality of decoding signals in response to a plurality of address signals, a first bias/ground selection control circuit for generating a plurality of first bias/ground selection signals determining bias conditions for a first group of the plurality of bit lines, a first bias/ground selection circuit for establishing bias conditions of the first group of the plurality of bit lines in response to the first bias/ground selection signals generated from the first bias/ground selection control circuit, a second bias/ground selection control circuit for generating a plurality of second bias/ground selection signals determining bias conditions of a second group of the plurality of bit lines, and a second bias/ground selection circuit for establishing bias conditions of the second group of the plurality of bit lines in response to the second bias/ground selection signals generated from the second bias/ground selection control circuit.

REFERENCES:
patent: 5886937 (1999-03-01), Jang
Mikiro Okada et al., "16Mb ROM Design Using Bank Select Architecture," Symposium on VLSI Circuits, pp. 85-86, Aug. 1988.

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