Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-30
2002-08-27
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S513000
Reexamination Certificate
active
06441427
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a nonvolatile semiconductor memory device such as a NOR-type flash memory and a method for manufacturing the same, and more particularly to the pattern construction of a memory cell array.
FIGS. 1A
to
1
D show the pattern construction of a memory cell array in a NOR-type flash memory as an example of the conventional nonvolatile semiconductor memory device.
FIG. 1A
is a pattern plan view,
FIG. 1B
is a cross sectional view taken along the
1
B—
1
B line of the pattern of
FIG. 1A
,
FIG. 1C
is a cross sectional view taken along the
1
C—
1
C line of the pattern of
FIG. 1A
, and
FIG. 1D
is a cross sectional view taken along the
1
D—
1
D line of the pattern of FIG.
1
A.
As shown in
FIGS. 1A
to
1
D, field oxide films (element isolation regions)
2
are formed on the main surface of a silicon substrate
1
by the LOCOS method. Source and drain regions
3
and
4
are separately formed on the surface areas of the silicon substrate
1
which are separated by the field oxide film
2
. Each source region
3
is formed of a pattern which is continuous in the row direction and commonly used by adjacent memory cells (cell transistors). A floating gate
6
is formed above the channel region between the source and drain regions
3
and
4
of each cell transistor with a tunnel oxide film
5
disposed therebetween. A control gate
8
is formed above the floating gate
6
with an insulating film
7
disposed therebetween. Each control gate
8
is formed to extend along the row direction to construct a word line. An inter-level insulating film
9
is formed on the stacked gate structure and bit lines
10
and common source lines
11
are formed on the inter-level insulating film
9
in a column direction which intersects the word lines (control gates)
8
. The common source line
11
is connected to the source regions
3
via through holes
13
in source contact portions
12
and the bit line
10
is connected to the drain regions
4
via through holes
14
.
In the NOR-type flash memory with the above structure, it is necessary to make contacts between the common source line
11
and the source regions
3
of the cell transistors in the pattern of the memory cell array. In this case, if formation of the through holes
13
in the inter-level insulating film and mask misalignment are taken into consideration, the patterns of the source regions
3
and common source line
11
in the source contact portions
12
must be made large or wide and the field oxide films (element isolation regions)
2
become different in the shape and interval thereof from the other region in the memory cell array. Therefore, the pattern formed when a slit for forming the floating gate
6
is formed becomes different in the interval thereof in the source contact portion
12
and in the memory cell section, and the pattern configuration of the word line
8
becomes different in some cases. As a result, repetitiveness with the regular interval of the pattern of the whole memory cell array is disturbed, and the etching process for forming the slits in this portion or the etching process for forming the word lines cannot be uniformly effected, thereby causing variations in various electrical characteristics for each memory cell thus formed, for example, the erasing characteristic by the F-N (Fowler-Nordheim) current and the programming characteristic by channel hot electrons. If the erasing characteristic is varied, the threshold voltage of the memory cell after erasing becomes negative, thereby causing a cell current to always flow irrespective of the word line potential. Therefore, if one of memory cells lying on the same bit line as the defective cell is selected, an erroneous reading operation may be effected.
As described above, the conventional nonvolatile semiconductor memory device and a method for manufacturing the same have a problem that the etching process becomes non-uniform and various electrical characteristics for each memory cell are varied since a portion in which repetitiveness with the regular interval of the pattern of the memory cell array is disturbed is present.
BRIEF SUMMARY OF THE INVENTION
Accordingly, a first object of this invention is to provide a nonvolatile semiconductor memory device capable of preventing a variation in the etching process due to the disturbance of repetitiveness with the regular interval of the pattern of the memory cell array and making the various electrical characteristics of each memory cell uniform.
A second object of this invention is to provide a method for manufacturing a nonvolatile semiconductor memory device capable of preventing a variation in the etching process due to the disturbance of repetitiveness with the regular interval of the pattern of the memory cell array and making the various electrical characteristics of each memory cell uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate and which has element regions isolated by element isolation regions of STI (Shallow Trench Isolation) structure, wherein the element isolation regions include a plurality of stripe-form trenches regularly arranged with substantially the same width and the same interval in an area from one end to the opposite end of the memory cell array and insulating films filled in the trenches.
With the above construction, since the plurality of trenches which form the element isolation regions of STI structure are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the pattern has the high degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate, wherein each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate between source and drain regions, a floating gate formed on the tunnel insulating film by isolating a silicon layer by use of plurality of stripe-form slits regularly formed with substantially the same width and the same interval in an area from one end to the opposite end of the memory cell array, an insulating film formed on the floating gate, and a control gate formed on the insulating film.
With the above construction, since the plurality of slits which form the floating gate by isolating the silicon layer are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the pattern of the memory cell array has the high degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate, wherein a plurality of stripe-form word lines regularly arranged with substantially the same width and the same interval in an area from one end to the opposite end of the memory cell array are provided.
With the above construction, since the plurality of word lines (control gates) are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the pattern of the memory cell array has the high degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device
Matsui Michiharu
Yamada Seiji
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Weiss Howard
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