NOR and NAND memory arrangement of resistive memory elements

Details NOR and NAND memory arrangement of resistive memory elements NOR and NAND memory arrangement of resistive memory elements

2007-04-19

2010-06-29

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S154000, C365S158000, C365S171000, C365S167000, C365S173000

Reexamination Certificate

active

07746683

ABSTRACT:
A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

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