Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-23
2004-05-11
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S321000
Reexamination Certificate
active
06734492
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for fabricating a semiconductor integrated circuit with a greater device density, and more particularly, to field-effect devices adapted for larger scales of integration and also to a method of fabricating such field-effect devices. A semiconductor device according to the invention is used especially advantageously as a nonvolatile semiconductor memory device having floating gates.
2. Description of the Related Art
Some conventional semiconductor devices are formed on a flat plane. Field-effect devices such as a MOS field-effect transistors (MOSFET) or a MISFET have a source, a drain, and a channel arranged substantially on a flat plane. The drain current is made to flow in a direction parallel to the substrate. In this planar device, however, limitations are imposed on the device area reduction as a matter of course. Therefore, in an attempt to obtain larger device densities, methods for manufacturing a planar device from plural layers and methods of fabricating a device structure itself in a form different from a planar structure have been discussed. An example of the latter methods includes a vertical-channel MOSFET proposed by us in Japanese Patent Unexamined Publication No. 13627/1994, which, in turn, corresponds to U.S. Pat. No. 5,350,937 and U.S. pending application Ser. No. 08/268,448, the disclosures of which are herein incorporated by reference. In particular, the drain is located over or under the source so that the drain current flows substantially vertically. This structure permits larger component densities. The above-cited Japanese Patent Unexamined Publication No. 13627/1994 pertains to a nonvolatile semiconductor memory. Specifically, a floating gate and a control gate are formed by anisotropic etching on side surfaces of elevated portions which are formed on a semiconductor substrate. It is to be noted, however, only the fundamental device structure is shown. Neither the whole memory construction nor the fabrication process is described in detail. For example, with respect to its peripheral circuit, few mentions are made of its structure and fabrication process.
SUMMARY OF THE INVENTION
The present invention is intended to address the foregoing problems with the prior art technique.
It is an object of the present invention to provide an improved NAND-type nonvolatile memory.
A method of fabricating a semiconductor device in accordance with the present invention comprises the steps of:
(1) burying an insulator for isolating device components in a semiconductor device;
(2) etching the semiconductor substrate and the insulator to form elevated portions;
(3) depositing an insulating film on exposed surface portions of the semiconductor substrate;
(4) forming a first conductive film;
(5) etching the first conductive film selectively and isotropically;
(6) anisotropically etching the first conductive film to form floating gates on side surfaces of the elevated portions;
(7) forming an insulating film on surfaces of the floating gates;
(8) forming a second conductive film; and
(9) anisotropically etching the second conductive film to form control gates on the side surfaces of the elevated portions so as to cover the floating gates.
The processing steps (5) and (6) may be interchanged in order. A doping step for diffusing dopants that impart one conductivity type may be carried out at any time as long as this step is performed later than the processing step (2). Furthermore, if multilevel metallization is utilized in the same way as in the prior art technique, an interlayer insulator is deposited after the processing step (9), and the top layer of metallization may be deposited.
The processing step (1) may use LOCOS (localized oxidation of silicon). Also, trench isolation technology which has attracted attention as a new device isolation technology may also be employed. In the processing steps (3) and (7), the insulating films may be formed by thermal oxidation, thermal nitridation, or CVD.
The first conductive film deposited by the processing step (4) will become floating gates after etching. Generally, as a result of the anisotropic etching of the step (6), the first conductive continuous film is left on one side surface of each elevated portion. If plural devices should be formed on each one side surface, it is necessary to isolate the floating gates of one device from the floating gates of other devices. For this purpose, the processing step (5) is carried out. In the step (5), the first conductive film on the side surfaces of the elevated portions is selectively etched. Then, the anisotropic etching of the step (6) is effected to obtain floating gates for the individual devices on each one side surface.
As mentioned previously, the processing steps (5) and (6) can be interchanged in order, because these two etching steps are independent steps which do not affect each other.
Where only vertical channel-type devices are fabricated, the order in which the doping processes are carried out presents no serious problems. However, if doping is done between the steps (2) and (4), the side surfaces of the elevated portions where channels should be formed might be doped. Therefore, the doping is preferably done after the processing step (4). If planar MOSFETs are formed at the same time, the doping is preferably carried out after the end of the processing step (9). Thus, the source and drain regions of the planar MOSFETs can be self-aligned to the gates.
While the novel fabrication process of the present invention has been described thus far as related to general cases, special cases are next described. A NAND-type nonvolatile memory is a promising application of the present invention. Where the novel fabrication process is applied to this NAND-type nonvolatile memory, care must be paid to device isolation technology. The technique of the above-cited Japanese Patent Unexamined Publication No. 13627/1994 is not limited to a NAND circuit. The NAND circuit has the disadvantage that ground lines must be laid parallel to the bit lines. However, the number of contacts to the top layer of metallization (in the case of a NAND circuit, bit lines and ground lines) per memory cell can be reduced.
In an ordinary NAND circuit, each individual memory block is composed of four or more, preferably eight or more, memory cells, or memory transistors. Each block is equipped with 2 selecting transistors. There exists one contact which brings the bit line into contact with the source of each selecting transistor, i.e., there are 2 contacts per block. The number of the contacts per block can be reduced to 1 by making any two adjacent blocks share a common contact. Where each block is composed of 4 or 8 memory cells, the number of the contacts per memory cell is ¼ or ⅛, respectively. On the other hand, in a normal matrix memory circuit, ground lines can be formed on a substrate and so the top layer of metallization can be formed into only bit lines, but at least one contact is necessary for each one memory cell. In this way, increasing the number of contacts makes it difficult to realize a higher device density.
The application of the present invention to a NAND circuit starts with the processing step (1), i.e., device isolation. During this processing step, an insulator used for the device isolation is required to be buried in a direction parallel to the bit lines. During the step (2), it is necessary to form trenches (i.e., linear elevated portions) parallel to the word lines. Let D be the depth of the insulator used for the device isolation in the processing step (1). Let d be the etch depth during the process step (2). The following relation must be met:
D−d>
0
This means that the bottom of the insulator is located deeper than the etching depth; otherwise device components would be coupled together in the direction of the word lines through the trenches formed by the processing step (2).
The device isolation is required for each bit line. Therefore, the insulator for the
Takemura Yasuhiko
Yamazaki Shunpei
Fish & Richardson PC
Semiconductor Energy Laboratory Co,. Ltd.
Smith Brad
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