Nonvolatile SRAM memory cell

Details Nonvolatile SRAM memory cell Nonvolatile SRAM memory cell

2007-02-27

2007-02-27

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S188000

Reexamination Certificate

active

10726263

ABSTRACT:
An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18′, 20′) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18′).

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International Search Report, FR 02 16558, dated Aug. 7, 2003.

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