Nonvolatile semiconductor storage device and operation...

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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C365S185190

Reexamination Certificate

active

07545684

ABSTRACT:
A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals. Further, the circuit for applying said plurality of pulse signals includes a first circuit for generating a first clock having a first amplitude voltage and a second clock having a second amplitude voltage which is higher than said first amplitude voltage, a second circuit for generating said plurality of said pulse signal having corresponding predetermined voltages based on said first clock or said second clock input from said first circuit respectively, and a third circuit for stopping an input of said first clock and said second clock to said second circuit when said plurality of pulse signals generated by said second circuit reach said corresponding predetermined voltages respectively.

REFERENCES:
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patent: 2002/0125935 (2002-09-01), Sawada et al.
patent: 2005/0174815 (2005-08-01), Chen et al.
patent: 7 169284 (1995-07-01), None
patent: 2000 76878 (2000-03-01), None
patent: 2001 57091 (2001-02-01), None
patent: 2004 274861 (2004-09-01), None
Hemink, et al., “Fast and Accurate Programming Mehtod for Multi-level NAND EEPROMs”. Symposium on VLSI Technology Digest of Technical Papers, p. 129-130, 1995.

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