Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-12-31
2000-08-29
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
G11C 2900
Patent
active
061123218
ABSTRACT:
A nonvolatile semiconductor storage device includes a repair request global flag for storing information indicating whether any faulty memory cell has been detected in the repair judgment test; and two tag memories, one for storing information indicating the word line associated with a faulty memory cell detected in the repair judgment test, the other tag memory storing bit line information associated with the detected faulty memory cell. A write state machine controls the data written to the repair request global flag and tag memories, and a write state machine algorithm storage section stores algorithms for which the write state machine executes a writing operation to the repair request global flag and tag memories.
REFERENCES:
patent: 5361343 (1994-11-01), Kosonocky et al.
patent: 5563828 (1996-10-01), Hasbun et al.
Murai Takashi
Shimada Kazuyuki
Chung Phung M.
Sharp Kabushiki Kaisha
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