Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-06-17
2003-05-20
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189110, C365S189060, C365S233100
Reexamination Certificate
active
06567319
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique especially effective for application to a nonvolatile memory having an internal booster, from which stored information can be electrically erased. For example, the invention relates to a technique effective for use in a flash memory employed for a portable electronic device.
In a portable electronic device, a volatile memory such as a DRAM and a nonvolatile memory such as a flash memory are used as memory devices of data. On the other hand, in a portable electronic device, a battery is used as a power source, and there is always a danger of occurrence of a dead battery. Due to this, in the portable electronic devices, a nonvolatile memory of which data is not erased even if the battery runs down is becoming the mainstream.
A flash memory uses, as a memory cell, a nonvolatile memory element comprising a MOSFET of a double gate structure having a control gate and a floating gate. By changing a fixed charged amount of the floating gate, a threshold voltage of the MOSFET is changed, thereby enabling information to be stored. Such a flash memory needs a high voltage (such as ±10V or higher) for changing the threshold voltage by pulling/injecting charges from/to the floating gate of the nonvolatile memory element in an operation of writing/erasing data to/from a memory cell. In the flash memory, the high voltage is generally generated by an internal booster provided in a memory chip.
SUMMARY OF THE INVENTION
In an operation of writing/erasing data to/from a memory cell in a flash memory having an internal booster, the internal booster is activated to boost an internal source voltage simultaneously with the start of the writing/erasing operation. After the internal source voltage is boosted to a predetermined voltage, a write voltage or an erase voltage is actually applied to a memory cell. Methods of determining a timing of starting an actual writing/erasing operation after the internal source voltage is boosted to a predetermined voltage include a method of determining the timing by monitoring a generated voltage and a method of determining the timing after elapse of a predetermined time on assumption that the internal source voltage has increased to the predetermined potential. In the former method, when the internal source voltage does not reach the predetermined potential for some reason, there is a fear that the program cannot escape from the writing or erasing operation. Conventionally, the latter method of determining the timing on the basis of time is generally employed.
In the method of determining the timing of actually applying the write voltage or erase voltage to the memory cell on the basis of time, however, the time required to boost the internal source voltage depends on the magnitude of an external source voltage, capability of the booster, and the load capacity of word line, bit line, or the like. The capability of the booster and the load capacity can be calculated from a designed circuit, and the external power source is determined in the specification. The timing is determined by calculating an expected time in which the internal source voltage is sufficiently boosted also in the case of performing the writing/erasing operation on a worst capacitor in the circuit in a state where a source voltage of the lower limit value determined in the specification (generally, a voltage lower than a source voltage used by about 10%) is applied.
In recent years, however, the variety of the external power source of the memory is increasing. For example, external power sources operating at 3.3V, 2.5V, 1.8V and the like are in demand. In a system using a memory, which is constructed on a substrate of a stay-at-home apparatus such as a personal computer, the source voltage is fixed. Consequently, there is no problem to determine the timing by calculating a time in which the internal source voltage is expected to be boosted by a booster with the source voltage (Vcc-10%) of the lower limit value determined by the specification. On the other hand, the memory used in the portable electronic device may operate on a DC voltage such as 3.3V converted from AC 100V, on a built-in battery of, for example, 1.8V, or the like.
In this case, even if 1.8V is supplied, when the timing is determined by calculating the time in which the internal source voltage is expected to be sufficiently boosted also in the case of performing the writing/erasing operation on the worst capacity in the circuit, the data writing/erasing operation can be performed with accuracy without a problem. In the case where the internal booster is constructed by using an MOSFET, however, when the operation voltage is 1.8V, the drain current of the MOSFET is about ¼ of that when the voltage is 3.3V. Consequently, the time required to boost the internal source voltage increases by four times. For example, the data writing operation is finished in 1 mS (millisecond) when the source voltage is 3.3V. It takes, however, 4 mS when the source voltage is 1.8V. In an actual product, the writing/erasing timing is determined on the basis of 1.8V with which the writing operation takes longer time even in the case where the external source voltage is 3.3V in consideration of the possibility where the product is used with the external source voltage of 1.8V. Consequently, a problem such that the time required for the writing/erasing operation when the external source voltage is 3.3V is long more than necessary occurs.
Further, the inventors of the present invention have found that the time required to boost the internal source voltage varies also according to a pattern of write data. Specifically, in association with an increase in packing density of a semiconductor memory, a bit line pitch of the memory array in a semiconductor memory is becoming very high. A parasitic capacitance between neighboring bit lines is becoming larger than a capacitance parasitic on a bit line, which exists between the bit line and the substrate, and a capacitance between the bit line and a line extending above the bit line.
Moreover, since the flash memory generally adopts a method of precharging a bit line in accordance with write data and simultaneously writing all of memory cells connected to one word line (hereinbelow, referred to as one sector), there is a case that 210 bit lines are precharged. In such a case, when all the write data of one sector is “0” or only one bit is “0” (since when all the write data is “1”, the writing operation is not performed), precharging against the parasitic capacitance between neighboring bit lines is not performed. When write data is 1010101 . . . 10, every other bit line is precharged, that is, the charging against all the parasitic capacitance between bit lines is performed. Consequently, the capacitive load on the booster is the heaviest in this case. By the deep examination on a flash memory being developed by the inventors of the present invention, it was found that a variation of about 1 mS at the maximum occurs in the boost time of the internal power source in accordance with the kind of write data.
In the conventional method of determining the write start timing on the basis of time, since the timing has to be determined by using the case of writing the data of “1010101 . . . 10” as the worst case regarding the data, the write start timing has to be further delayed. It was clarified that, when the timing is determined in consideration of the worst case with the source voltage of 1.8V, a time allowance of about five times as long as the time necessary to boost the power source voltage to write data of all “0” with the source voltage of 3.3V is necessary, so that the write time takes very long.
The inventors then examined the method of monitoring not time but a boosted internal source voltage and, when the internal source voltage reaches a predetermined potential, starting the writing operation. In this case, however, when the internal source voltage does not reach the predetermined potential by the cause such as a leak due to ad
Kubono Shoji
Manita Kiichi
Noda Satoshi
Sato Hiroshi
Shigematsu Koji
Lam David
Miles & Stockbridge P.C.
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