Nonvolatile semiconductor memory with a page mode

Details Nonvolatile semiconductor memory with a page mode Nonvolatile semiconductor memory with a page mode

2002-09-05

2004-08-24

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S230010, C365S230030, C365S230060, C365S230080, C365S235000

Reexamination Certificate

active

06781879

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-269423, filed Sep. 5, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory, such as a flash memory, and more particularly to an address allocating method for a nonvolatile semiconductor memory with a page mode (page reading function).
2. Description of the Related Art
One known nonvolatile semiconductor memory is a flash memory.
FIG. 1
is a sectional view of a memory cell in the flash memory. The memory cell (or memory cell transistor) is composed of a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), which has a stacked-gate structure where a floating gate FG and a control gate CG are stacked on top of the other via an insulating film. Specifically, in this example, an N-well region
101
is formed in a P-substrate. In the N-well region
101
, a P-well region
102
is formed. At the surface of the P-well region
102
, an n
+
-type impurity diffused region
103
acting as the drain region of the MOSFET, an n
+
-type impurity diffused region
104
acting as the source region, and a p
+
-type impurity diffused region
105
are formed. On the substrate
100
between the impurity diffused regions
103
and
104
, a gate insulating film
106
, a floating gate FG, an insulating film
107
, and a control gate CG are stacked in that order. At the surface of the N-well region
101
, there is provided an n
+
-type impurity diffused region
108
, which is connected to the impurity diffused region
104
and impurity diffused region
105
. In addition, at the main surface of the substrate
100
, there is provided a p
+
-type impurity diffused region
109
, which is then connected to the ground point.
In the memory cell transistor, the threshold voltage with respect to the control gate CG changes (or shifts) according to the number of electrons accumulated in the floating gate FG. The memory cell transistor stores “0” or “1” data according to a change in the threshold voltage.
FIG. 2
shows a part of a memory cell array where units of the memory cell transistor are arranged in a matrix. The control gates of the individual memory cell transistors MC are connected to word lines WL
0
to WLn on a row basis. The drains of the individual memory cell transistors MC are connected to bit lines BL
0
to BLm on a column basis. The sources of the individual memory cell transistors MC are all connected to a ground point Vss (source line).
FIG. 3
shows the relationship between the control gate voltage and the drain current in the memory cell transistor of
FIG. 1. A
state where the number of electrons accumulated in the floating gate FG is relatively large (that is, the threshold voltage Vt of the memory cell transistor is high) is defined as “0” data. Conversely, a state where the number of electrons accumulated in the floating gate FG is relatively small (that is, the threshold voltage Vt of the memory cell transistor is low) is defined as “1” data. The bias conditions for data reading, erasing, and writing are shown in TABLE 1:
TABLE 1
Read
Program
Erase
Vg
5 V
9 V
 −7 V
Vd
1 V
5 (“0”)
Floating
0 (“1”)
Vs
0 V
0 V
  10 V
The data is read by applying voltage Vd (=1 V) to the drain of the memory cell transistor, voltage Vs (=0 V) to the source, and voltage Vg (=5 V) to the control gate CG. Whether the stored data is “1” or “0” is determined, depending on whether cell current Icell flows or not.
Erasing is effected all at once on the memory cells that share the source and the P-well region
102
. When the drain is set in the floating state, the source voltage Vs is set to Vs=10 V, and the control gate voltage Vg is set to Vg=−7 V, electrons flow from the floating gate FG to the substrate because of an F-N tunnel phenomenon, which sets all of the memory cells to be erased to “1” data.
In contrast, writing is done bit by bit. In a state where the source voltage Vs is set to Vs=0 V and the control gate voltage Vg is set to Vg=9 V, a 5 V bias (drain voltage Vd=5 V) is applied to the bit line of the cell into which “0” is to be written, which causes high-energy electrons generated in a channel hot electron phenomenon to be injected into the floating gate. At this time, when the bit line to be kept at “1” is set to 0 V (drain voltage Vd=0 V), this prevents electrons from being injected, resulting in no change in the threshold voltage Vt.
Next, to check the program or erase operation, program verify or erase verify is performed. In the program verify, the control gate voltage Vg is set to a voltage Vpv higher than that in reading, thereby performing “0” reading. Then, a write operation and a program verify operation are carried out alternately. When all of the cells to be written into have the “0,” the writing operation is ended. Similarly, in erasing, a voltage Vev lower than the voltage in reading is applied to the control gate CG, thereby carrying out a “1” reading erase verify operation, which secures the cell current Icell sufficiently. As described above, the word-line voltage to the cell varies according to the operation mode.
With the recent improvements in the data processing speed of CPUs (Central Processing Units), flash memories are required to have higher-speed data transmission speed. Such flash memory as shortens the total data output time of consecutive words by having a page mode reading function as DRAM or SRAM has been put on the market (see ISSCC2001 DIGEST OF TECHNICAL PAPERS pp. 32-33, February 2001, B. Pathank et al., “A 1.8-V 64-Mb 100-MHz Flexible Read While Write Flash Memory”). A collection of words, that is, a page, is specified by a page address. Any word on the page is specified by an intra-page address (in-page address). Since words on the page have consecutive addresses, the intra-page addresses are allocated to the column side. Therefore, in a case where low-order addresses are allocated to the column side, addresses higher in order than these addresses are allocated to the row side, and addresses still higher in order are allocated to block addresses, when a program composed of several tens of to hundreds of consecutive words is read, the number of word lines to be selected is smaller than that in a conventional method of allocating low-order addresses to the row side, middle-order addresses to the column side, and high-order addresses to block addresses. As a result, the time during which reading stress per line is applied becomes longer, which makes it more difficult to maintain the data reliability.
For example, when cells for 32 words are connected to a single word line, consider a case where 128 words continue to be read for ten years. When there is no page mode function, since allocating the low-order addresses to the rows makes it possible to read 128 word lines equally, the stress time per word line is 3×10
8
sec/128 words=3×10
6
sec. On the other hand, when the page size is 8 words, four pages are allocated to a single word line and 128 words are allocated to four word lines. As a result, since eight words can be read during the time required to read one word, the word line stress time with respect to the time required to read eight words is ⅛. However, because the number of word lines decreases to {fraction (4/128)}, the length of time that a single word line is selected becomes 32 times the present value. As a result, the word line stress time (or read disturb time) is four times as long as that when there is no page mode.
As described above, the conventional nonvolatile semiconductor memory with a page mode reading function to realize high-speed data transfer speed has the problem of increasing the read disturb time. Measures to deal with this problem have been needed.
BRIEF SUMMARY OF THE INVENTION
According to an aspe

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