Nonvolatile semiconductor memory with a floating gate that has a

Details Nonvolatile semiconductor memory with a floating gate that has a Nonvolatile semiconductor memory with a floating gate that has a

1996-07-31

1999-10-05

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257321, H01L 29788

Patent

active

059628898

ABSTRACT:
In the nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix of the present invention, the memory cell array includes: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; floating gates formed on the tunnel oxide film; first insulating films formed on the floating gates; and control gates formed on the first insulating films, wherein each of the floating gates includes a first polysilicon film and second polysilicon films, the second polysilicon films being formed on both sides of the first polysilicon film, second insulating films are formed on the tunnel oxide film between the first polysilicon films, the second insulating films having a predetermined thickness which is thinner than that of the first polysilicon films, and the second polysilicon films are formed on the second insulating films.

REFERENCES:
patent: 4115914 (1978-09-01), Harari
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 4945068 (1990-07-01), Sugaya
patent: 4989054 (1991-01-01), Arima et al.
patent: 5019879 (1991-05-01), Chiu
patent: 5021848 (1991-06-01), Chiu
patent: 5140551 (1992-08-01), Chiu
patent: 5273923 (1993-12-01), Ko-Min et al.
patent: 5283758 (1994-02-01), Nakayama et al.
patent: 5379254 (1995-01-01), Chang
patent: 5471080 (1995-11-01), Satoh et al.
patent: 5516713 (1996-05-01), Chen-Chiu et al.
patent: 5521110 (1996-05-01), Manzur
patent: 5569946 (1996-10-01), Hong
patent: 5621233 (1997-04-01), Sharma et al.
patent: 5637897 (1997-06-01), Oyama
patent: 5675162 (1997-10-01), Hong
Yoshikawa et al., "An Asymmetrical Lightly Doped source Cell For Virtual Ground High-Density Eprom's", IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1, 1990, pp. 1046-1051, XP000125218.
Ohi et al., "An Asymmetrical Offset Source/Drain Structure For Virtual Ground Array Flash Memory with Dinor Operation", Digest of Technical Papers of the Symposium on VLSI Technology, Kyoto, May 17-19, 1993, No. -, May 17, 1993, Institute of Electrical and Electronics Engineers, pp. 57/58, XP000462904.
Hisamune et al, IEDM 93, "A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories", pp. 19-22, 1993.
Kato et al, IDEM 94, "A 0.4-.mu.m.sup.2 Self-Aligned Contactless Memory Cell Technology Suitable for 256-Mbit Flash Memories", 1994, pp. 921-923.

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory with a floating gate that has a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory with a floating gate that has a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory with a floating gate that has a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1174467