Nonvolatile semiconductor memory system with a plurality of eras

Details Nonvolatile semiconductor memory system with a plurality of eras Nonvolatile semiconductor memory system with a plurality of eras

1993-06-17

1994-12-20

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Data refresh

365218, 365185, 36523003, H01L 2976

Patent

active

053750942

ABSTRACT:
A nonvolatile semiconductor memory system including a memory cell array (1) having a plurality of floating gate memory cell transistors (MC) arranged in a matrix of rows and columns with plurality of bit lines (BL) connected to the drains of the floating gate memory cell transistors arranged in a same column and a plurality of word lines (WL) connected to the control gates of the floating gate memory cell transistors in a same row, and a refresh circuit for periodically refreshing the stored data in the floating gate memory cell transistor.

REFERENCES:
patent: 4617660 (1986-10-01), Sakamoto
Semiconductor Memories Second Edition, Betty Prince, John Wiley & Sons, pp. 319-321 and 589-594.

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