Nonvolatile semiconductor memory including two memory cell...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S316000, C257S319000

Reexamination Certificate

active

10892445

ABSTRACT:
This nonvolatile semiconductor memory includes: a first and a second memory cell column having memory cell transistors connected in series with a floating gate and a first and a second control gate located at both sides of that floating gate; a first select-gate transistor connected between the first memory cell column and a bit line; a second select-gate transistor connected between the second memory cell column and the bit line; and a third select gate transistor connected between the first memory cell column and a source line and also between the second memory cell column and the source line, respectively.

REFERENCES:
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patent: 2005/0073001 (2005-04-01), Kamigaichi et al.
patent: 6-325580 (1994-11-01), None
patent: 6-325581 (1994-11-01), None
patent: 7-193199 (1995-07-01), None
patent: 2002-280463 (2002-09-01), None
U.S. Appl. No. 11/450,355, filed Jun. 12, 2006, Kutsukake et al.
U.S. Appl. No. 11/563,069, filed Nov. 24, 2006, Kamigaichi et al.
U.S. Appl. No. 11/565,843, filed Dec. 1, 2006, Arai et al.
U.S. Appl. No. 11/566,283, Dec. 4, 2006, Arai et al.
U.S. Appl. No. 11/550,636, Oct. 18, 2006, Arai et al.

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