Nonvolatile semiconductor memory in which the number of...

Details Nonvolatile semiconductor memory in which the number of... Nonvolatile semiconductor memory in which the number of...

2000-06-13

2001-04-24

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185230

Reexamination Certificate

active

06222773

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a nonvolatile semiconductor memory and more particularly to an electrically erasable programmable semiconductor memory (EEPROM) which can be used in a NOR type flash memory, for example.
As an EEPROM including memory cells each of which has a gate structure having a floating gate and a control gate stacked thereon to store data “0” or “1” in a nonvolatile fashion by changing the number of electrons stored in the floating gate, a NOR type flash memory is known, for example. The flash memory includes a memory cell array having memory cells arranged in an array form and data stored in the memory cells can be simultaneously erased for the whole memory cell array or for each block unit.
This type of NOR type flash memory is described in IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. 27, NO. 11, NOVEMBER 1992 pp. 1540-1545, Umezawa et al. “A 5-V-Only Operation 0.6 &mgr;m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure” and IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. 27, NO. 11, NOVEMBER 1992 pp. 1547-1553, Jinbo et al. “A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode”, for example.
FIGS. 1A
to
1
C schematically show the structure of the memory cell in the NOR type flash memory.
FIG. 1A
is a pattern plan view,
FIG. 1B
is a cross sectional view taken along the
1
B—
1
B line of FIG.
1
A and
FIG. 1C
is a cross sectional view taken along the
1
C—
1
C line of FIG.
1
A.
As shown in
FIGS. 1A
to
1
C, an N-type well
1
b
is formed in a P-type semiconductor substrate
1
a
and a P-type well
1
c
for forming a cell area is formed in the N-type well
1
b.
A cell array is formed on the P-type well
1
c.
An element isolation insulating film
2
is disposed over the main surface of the substrate
1
a
to electrically isolate the memory cells. A gate oxide film
3
is formed over the main surface of the substrate
1
a
(on the P-type well
1
c
) isolated by the element isolation insulating film
2
. A floating gate
4
of each cell is formed on the gate oxide film
3
of the cell. An insulating film (an insulating film between the floating gate and the control gate)
6
is formed on the floating gate
4
. A control gate
5
of the cell is formed on the insulating film
6
to cover the floating gates of the adjacent cells. An inter-level insulating film
7
is formed on the resultant semiconductor structure. A bit line
8
is formed on the inter-level insulating film
7
to extend in a direction intersecting the control gate
5
. A drain region (n-type diffusion layer)
9
and a source region (n-type diffusion layer, source line)
10
of the cell are separately formed in the P-type well
1
c
below the stacked gate structure. A through hole
12
is formed in the inter-level insulating film
7
on the drain region
9
to permit the drain region
9
and the bit line
8
to be connected at a bit contact portion
11
.
As described above, the memory cell has the drain
9
, source
10
, floating gate
4
and control gate
5
and stores data by changing the amount of charges stored in the floating gate
4
.
FIG. 2
is a circuit diagram showing an example of the construction of a memory cell array having memory cells which are the same in construction as the memory cell shown in
FIGS. 1A
to
1
C arranged in a matrix form.
The gate electrodes of memory cells MC
00
to MCn
0
, MC
01
to MCn
1
, . . . , or MC
0
m to MCnm on the same row are connected to a corresponding one of word lines WL
0
to WLn, the drain electrodes thereof on the same column are connected to a corresponding one of bit lines BL
0
to BLm, and the source electrodes thereof are commonly connected to a source line SL.
Among the NOR type flash memory, a memory of plural-bit configuration for simultaneously inputting/outputting data of plural bits with respect to the exterior at the time of data programming/data readout is provided and a memory of 16-bit configuration having the bit width of 16 is known as one example.
In the NOR type flash memory of plural-bit configuration, the same cell array block is divided into N groups in the unit of plural columns. Memory cells of the N groups are selected by use of the same row selection signal at the time of data readout/data programming and one memory cell is selected from the memory cells of each of the N groups by use of a column selection signal so that N memory cells can be simultaneously selected.
FIG. 3
shows an extracted part of the cell array block in the NOR type flash memory of plural-bit configuration and an extracted part of a peripheral circuit associated therewith.
Bit lines are divided into groups BL
0
to BL
15
, . . . each including four bit lines, for example, one-side ends of the current paths of column selection transistors CS are respectively connected to one-side ends of the four bit lines of each of the groups BL
0
to BL
15
, . . . and the other ends of the current paths of the four column selection transistors CS are commonly connected to make a common bit line. The common bit line is connected to one end of a bit line load (bit line load transistor) LT, an input terminal of a sense amplifier SA, one end of the current path of a programming transistor WT and the like via the current path of a bit line potential clamping transistor CT. The other ends of the current paths of the bit line load transistor LT and programming transistor WT are connected to power supplies.
In the NOR type flash memory of plural-bit configuration, each of the bit lines BL
0
to BL
15
and BL
16
to BLm in
FIG. 2
corresponds to one of the four bit lines of each of the groups BL
0
to BL
15
, . . .
When data re-programming is effected for a memory cell in the NOR type flash memory, in order to prevent occurrence of a phenomenon (disturb at the time of re-programming of data) that another memory cell commonly using the bit line or word line with the memory cell for data re-programming is set into a half-selected state and the data storing state thereof is changed, the word line/bit line is separated for each block unit to be erased. The block unit to be erased is generally 512 kbits and, for example, a cell block array of 1 k word lines×512 bit lines configuration or 512 word lines×1 kbit lines configuration is used.
Next, the data programming, readout and erasing operations in the NOR type flash memory with the above construction are explained.
(1) When the memory cells MC
00
to MC
015
are selected at the time of data programming, a voltage of Vpp (a voltage of approx. 10V) is applied to the selected word line WL
0
commonly used by the memory cells MC
00
to MC
015
and the other non-selected word lines WL
1
to WLn are set to 0V.
Bit line voltages applied to the selected bit lines BL
0
to BL
15
respectively connected to the selected memory cells MC
00
to MC
015
depend on programming data, and Vdp (a voltage of approx. 5V) is applied to the bit line corresponding to data “0” to be programmed and 0V is applied to the bit line corresponding to data “1” to be programmed. The source line SL is set at 0V.
Thus, in the selected memory cell into which data “0” is programmed among the selected memory cells MC
00
to MC
015
, the gate is set at Vpp and the drain is set at Vdp. Among the electrons moving from the source to the drain, some electrons have a large amount of energy so as to reach the floating gate by the electric field in the gate direction. Then, the “1” data state in which the number of electrons in the floating gate is relatively small is changed into the “0” data state in which the number of electrons in the floating gate is relatively large.
In the memory cells having the gate voltage-drain voltage relation different from the above relation (in the non-selected memory cell and the selected memory cell into which “1” data is programmed), no drain current flows and data in the memory cell is not changed.
(2) When the memory cells MC
00
to MC
015
are selected at the time of data readout, Vcc (a voltage of approx. 5V) is applied to the selected word line WL
0
commonly used by the above m

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