Nonvolatile semiconductor memory having sub-arrays formed within

Details Nonvolatile semiconductor memory having sub-arrays formed within Nonvolatile semiconductor memory having sub-arrays formed within

1997-11-05

1999-03-23

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular connection

36518501, 36518717, 257315, 257316, G11C 1134, H01L 29788

Patent

active

058869247

ABSTRACT:
Disclosed is a nonvolatile electrically-erasable semiconductor memory having an array of storage cells divided into sub-arrays, where the memory is formed on a semiconductor substrate doped with a first type of conductive impurity having a first well doped with a second type of conductive impurity. The storage cells for each sub-array are formed in a pocket well formed in the first well and doped with the first type of conductive impurity. A programming operation is performed by applying a programming voltage, such as 18 V, to the control gates of only those storage cells that are selected to be programmed, applying a ground level voltage to the pocket well corresponding to the selected storage cells, and applying an anti-programming voltage, such as 7 V, to the pocket wells corresponding to the storage cells that are not selected for programming. An erasing operation is performed by applying a ground level voltage to the control gates of the storage cells selected for erasure, applying an erasing voltage, such as 20 V, to the pocket well corresponding to the selected storage cells, and applying a prescribed voltage, such as from 4 V to 14 V, to the pocket wells corresponding to the storage cells that are not selected for erasure.

REFERENCES:
patent: 4878199 (1989-10-01), Mizutani
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5677556 (1997-10-01), Endoh
patent: 5751631 (1998-05-01), Liu et al.

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