Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-08-30
2003-12-30
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185120, C365S185130, C365S230030
Reexamination Certificate
active
06671203
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-265022, filed Aug. 31, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory such as a flash memory and, more particularly, to a nonvolatile semiconductor memory having a page mode (page read function) with a plurality of banks.
2. Description of the Related Art
A flash memory is known as one of nonvolatile semiconductor memories.
FIG. 1
is a sectional view showing the memory cell of the flash memory. This memory cell (memory cell transistor) is constituted by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a so-called stacked gate structure in which a floating gate FG and control gate CG are stacked via an insulating film. In this example, an N-well
101
is formed in a P-semiconductor substrate (P-substrate)
100
, and a P-well
102
is formed in the N-well
101
. An N
+
-impurity diffusion region
103
serving as the drain region of the MOSFET, and an N
+
-impurity diffusion region
104
and P
+
-impurity diffusion region
105
serving as the source region of the MOSFET are formed in the surface region of the P-well
102
. A gate insulating film
106
, floating gate FG, insulating film
107
, and control gate CG are stacked on the substrate
100
between the impurity diffusion regions
103
and
104
. An N
+
-impurity diffusion region
108
is formed in the surface region of the N-well
101
. The impurity diffusion region
108
is connected to the impurity diffusion regions
104
and
105
. A P
+
-impurity diffusion region
109
is formed in the major surface of the substrate
100
, and grounded.
The memory cell transistor changes (or shifts) the threshold voltage viewed from the control gate CG in accordance with the number of electrons accumulated in the floating gate FG. The memory cell transistor stores data “0” or “1” in accordance with a change in threshold voltage.
FIG. 2
shows part of a memory cell array in which memory cell transistors are arrayed in a matrix. The control gates of memory cell transistors MC on respective rows are connected to word-lines WL
0
to WLn. The drains of the memory cell transistors MC on respective columns are connected to bit-lines BL
0
to BLm, and their sources are commonly connected to a ground point Vss (source-line).
FIG. 3
shows the relationship between the control gate voltage (gate voltage) and drain current of the memory cell transistor shown in FIG.
1
. In
FIG. 3
, a state in which the number of electrons accumulated in the floating gate FG is relatively large (i.e., a threshold voltage Vt of the memory cell transistor is high) is defined as “0” data, and a state in which the threshold voltage Vt is low is defined as “1” data. Data read, erase, and program bias conditions are shown in Table 1.
TABLE 1
Read
Program
Erase
Vg
5 V
9 V
−7 V
Vd
1 V
5 (“0”)
Floating
0 (“1”)
Vs
0 V
0 V
10 V
Data is read by applying the voltage Vd (=1 V) to the drain of the memory cell transistor, the voltage Vs (=0 V) to the source, and the voltage Vg (=5 V) to the control gate. Whether stored data is “1” or “0” is determined by whether a cell current Icell flows.
Erase is executed at once for a plurality of memory cells which share the source and P-well
102
. The drain is changed to the floating state, and the source voltage Vs=10 V and the control gate voltage Vg=−7 V are set. Then, electrons flow from the floating gate FG to the substrate by the F-N tunnel phenomenon, and all the memory cells subjected to erase are set to “1” data.
To the contrary, program is done every bit. While the source voltage Vs=0 V and the control gate voltage Vg=9 V are set, 5 V is biased (drain voltage Vd=5 V) to the bit-line of cells in which “0” is to be written. High-energy electrons generated by the channel hot electron phenomenon are injected into the floating gate. At this time, by setting the bit-line of cells kept at “1” to 0 V (drain voltage Vd=0 V), no electron injection occurs and the threshold voltage Vt does not change.
In order to confirm program or erase, program verify or erase verify is performed. Program verify performs “0” read by setting the control gate voltage Vg to a voltage Vpv higher than the read voltage. Program and program verify are alternately executed, and when all cells to be programmed change to “0”, program operation ends. Similarly, during erase, a voltage Vev lower than the read voltage is applied to the control gate CG to execute erase verify which performs “1” read, and a sufficient cell current Icell is ensured. In this manner, the word-line voltage of the cell changes depending on the operation mode.
The reprogram time of the flash memory is longer than the read time by several orders of magnitude. To solve this problem, a so-called dual operation function has been introduced (e.g., U.S. Pat. Nos. 5,867,430 and 5,847,998). According to this function, the flash memory is divided into two banks or more. Even if a given bank undergoes reprogram, cell data can be read out from another bank. With the improvement of the MPU (Micro Processing Unit) performance, a higher read rate of the flash memory becomes important. Under these circumstances, a technique of greatly shortening the average access time by using page and burst modes has been available.
A 64-Mbit flash memory described in B. Pathank et al., “A 1.8V 64 Mb 100 MHz Flexible Read While Write Flash Memory”, ISSCC2001 DIGEST OF TECHNICAL PAPERS pp. 32-33, February, 2001 comprises 16 4-Mbit banks, and has a 4-word page-length page access function. This flash memory adopts row decoders for respective banks in order to enable the banks to independently operate.
This arrangement means a large-size decoder area overhead, resulting in high chip cost.
As described above, the conventional nonvolatile semiconductor memory suffers a longer reprogram time than the read time by several orders of magnitude. Increasing the reprogram time leads to a large-size decoder area overhead and high chip cost.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising first and second nonvolatile memory banks, a data-line for read and a data-line for program and verify which are arranged in a region between the first and second nonvolatile memory banks and selectively connected to bit-lines of the first and second nonvolatile memory banks, a sense amplifier for read connected to the data-line for read, a sense amplifier for program and verify connected to the data-line for program and verify, and a program circuit connected to the data-line for program and verify.
According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising a nonvolatile memory block matrix in which a plurality of nonvolatile memory blocks are arrayed in a matrix in X and Y directions, each of the plurality of nonvolatile memory blocks having a first nonvolatile memory element, a first word-line and a first bit-line connected to the first nonvolatile memory element, a first row decoder connected to the first word-line, a first column decoder connected to the first bit-line, and a block decoder connected to the first row decoder and the first column decoder; a second word-line connected to the first row decoder; a second bit-line connected to the first column decoder; a second row decoder connected to the second word-line; second and third column decoders connected to the second bit-line; a first data-line connected to the second column decoder; a second data-line connected to the third column decoder; a first sense amplifier connected to the first data-line; and a second sense amplifier connected to the second data-line.
REFERENCES:
patent: 5581503 (1996-12-01), Matsubara et al.
Atsumi Shigeru
Shiga Hitoshi
Takano Yoshinori
Tanzawa Toru
Taura Tadayuki
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