Nonvolatile semiconductor memory having page mode programming fu

Details Nonvolatile semiconductor memory having page mode programming fu Nonvolatile semiconductor memory having page mode programming fu

1988-10-28

1990-07-24

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

3652385, G11C 1140

Patent

active

049439626

ABSTRACT:
A nonvolatile semiconductor memory of this invention is constituted to latch input data into data latch circuits and at the same time control the programming operation of the bit line load transistors when the chip enable signal is made active and a page programming power source voltage is set at the programming voltage, while the output enable signal is kept inactive. Further, when the output enable signal is made active or the programming power source voltage is set at a voltage different from the programming voltage, the data latch circuits are reset. The data latch circuits can be selectively specified by a preset combination of bits.

REFERENCES:
patent: 4685084 (1987-08-01), Canepa
M. Fukuda et al., 1 M bit CMOS EPROM "HN27C101"/HN27C301.
T. Hagiwara et al., "Page Mode Programming 1 Mb CMOS EPROM," 1985 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 174-175.

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