Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-03-19
2002-05-07
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185200
Reexamination Certificate
active
06385112
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices and particularly relates to flash memory devices that perform verify operations.
2. Description of the Related Art
In flash memory devices, verify operations are necessary to ascertain that electric charges are properly injected to memory cells by program operations. If the verify operations failed, program operations are repeated until results of verify operations are found successful, that is, “pass”. In case of erase operations, verify operations are performed similarly to ascertain proper removal of the electric charges from the memory cells.
Recently, main implementations have been such that a read operation and a program/erase operation are performed simultaneously in flash memories. In such implementations, verify operations are subjected to noise in power supply lines, which is generated by the data read operation, causing erroneous checks. The erroneous checks result from identifying a “fail” state as a “pass” state, for example. That is, a state which should have been determined as “fail” and for which program or erase operations should have been repeated for sufficient charging or discharging, may be erroneously determined as “pass” and the program or erase operations are considered as completed because of the power line noise. In this manner, an erroneous operation may occur during data reading operations.
Accordingly, there is a need for a semiconductor memory device which does not malfunction during the verify operation even if there is a power line noise or the like.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
A specific object of the present invention is to provide a semiconductor memory device that performs error-free verify operations which have been adversely affected by noise in conventional implementations.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor memory device including:
a memory cell;
a comparator unit that detects whether a first level corresponding to a memory status of the memory cell is set within a predetermined range based on comparison of the first level with a reference level; and
a dummy cell that provides a second level which is set to such a level that the comparator unit determines the second level as falling outside the predetermined range when comparing the second level with the reference level.
In the present invention, if the comparator unit determines that the second level is within the predetermined range based on comparison with the reference level, it determines that there is an error.
Further, if the comparator unit determines that the second level is outside the predetermined range and if the first level is within the predetermined range, it determines that the first level is correctly set at a proper range.
In case where the comparator unit detects that the second level is within the predetermined range based on comparison with the reference level and that the first level is set within the predetermined range, it ascertains that the first level is not correctly set within the predetermined range.
As above described, the present invention provides a dummy cell which is set such as to fail in the verify operation under normal conditions, i.e., in the absence of disturbing noise. The voltage of the dummy cell is affected when the voltage of data cells is affected by the noise, which makes the dummy cell voltage pass the verification test, which means that there has been an erroneous determination.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5157626 (1992-10-01), Watanabe
patent: 6163484 (2000-12-01), Uekubo
patent: 6172911 (2001-01-01), Tanaka
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Zarabian A.
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