Static information storage and retrieval – Read/write circuit – Signals
Patent
1983-08-29
1986-02-18
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Signals
365184, 365233, 357 235, G11C 700, G11C 1140
Patent
active
045717052
ABSTRACT:
A nonvolatile semiconductor memory device has a memory cell array including a MOS FET with a floating gate, first and second control gates and a program electrode; column and row decoders for selecting a specific memory cell; a program control circuit for programming data on the floating gate; and a timing circuit for providing operation timings of the column and row decoders and the program control circuit. The timing circuit sets up a program inhibit period ranging over time point at which a selected memory cell is to be erased and programmed. In the program inhibit period, one of the first and second control gates of each of the memory cells is at a high potential, while the other control gate is at low potential.
REFERENCES:
patent: 3728695 (1973-04-01), Frohman-Bentchkowsky
patent: 4110842 (1978-08-01), Sarkissian et al.
patent: 4314265 (1982-02-01), Simko
patent: 4334292 (1982-06-01), Kotecha
patent: 4344154 (1982-08-01), Klaas et al.
patent: 4377857 (1983-03-01), Tickle
patent: 4393481 (1983-07-01), Owen et al.
patent: 4398269 (1983-08-01), Hedin et al.
Gossage Glenn A.
Hecker Stuart N.
Toyko Shibaura Denki Kabushiki Kaisha
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