Nonvolatile semiconductor memory device with a row redundancy ci

Details Nonvolatile semiconductor memory device with a row redundancy ci Nonvolatile semiconductor memory device with a row redundancy ci

1995-06-06

1997-02-11

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular connection

365200, 36518523, G11C 1134

Patent

active

056027788

ABSTRACT:
A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

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patent: 4999813 (1991-03-01), Ohtsuka et al.
Digital Kairo No Kiso, Saito et al., Tokai Daigaku Shuppan Kai, pp. 8-12.
A New Erasing and Row Decoding Scheme For Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories, Yoshikazu Miyawaki et al., IEEE Journal of Solid State Circuits, vol. 27, No. 4, Apr. 1992, pp. 583-588.

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