Nonvolatile semiconductor memory device with a lightly-doped dra

Details Nonvolatile semiconductor memory device with a lightly-doped dra Nonvolatile semiconductor memory device with a lightly-doped dra

1987-04-24

1988-11-29

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365189, 357 235, G11C 1134, G11C 700, H01L 2978

Patent

active

047886633

ABSTRACT:
Each memory cell in an EPROM includes two memory cell transistors which share a common floating gate and have two separated drains, one of which is connected to a read bit line and the other of which is connected to write bit line. In this EPROM, the read memory cell transistor of the read bit line has a lower hot electron injection rate than the hot electron injection rate of the write memory cell transistor of the write bit line. A bit line voltage booster is connected to the read bit line.

REFERENCES:
patent: 4628487 (1986-12-01), Smayling
patent: 4663740 (1987-05-01), Ebel
Pathak et al., "A 25ns 16K CMOS PROM Using a 4-Transistor Cell," IEEE International Solid-States Circuits Conference, pp. 162.varies.163, Feb. 14, 1985.
Pathak et al., "A 25-ns 16K CMOS PROM Using a Four-Transistor Cell and Differential Design Techniques," IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, pp. 964-970, Oct. 1985.

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