Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-03
2003-03-11
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S319000
Reexamination Certificate
active
06531732
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, a process of manufacturing the same and a method of operating the same. In particular, it relates to an electrically writable and erasable nonvolatile semiconductor memory device having a charge accumulating region, a process of manufacturing the same and a method of operating the same.
2. Description of Related Art
As one of nonvolatile semiconductor memory devices, there has been known a 2-bit flash cell of MONOS (Metal Oxide Nitride Oxide Semiconductor) type referred to as NROM in which charges are accumulated in an ONO film comprising a layered structure of an oxide film/a nitride film/an oxide film (Boaz Eitan et al., Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, pp. 522-523).
FIGS.
17
(
a
) and
17
(
b
) shows a structure of the NROM cell in which a gate insulating film
30
in an n-channel MOSFET is replaced with an ONO film comprising a silicon nitride film
31
as a charge accumulating material sandwiched between two silicon oxide films
32
and
33
. The silicon oxide films
32
and
33
sandwiching the silicon nitride film
31
each have a thickness of about 50 Å or more to avoid a direct tunneling phenomenon. The NROM cell shows a virtually grounded structure and thus a bit line
34
functions as a source of one transistor and a drain of another transistor.
In the NROM cell, accumulated charges are detected as physically separated two bits in accordance with a particular method described below.
To write data in a bit
1
(b
1
) shown in FIGS.
17
(
a
) and
17
(
b
), voltages of 0V, 4.5V and 9V are applied to a bit line
2
(BL
2
), a bit line
1
(BL
1
) and a word line (WL), respectively, to turn the MOSFET on. Accordingly, electrons are injected and accumulated in the silicon nitride film
31
near the bit line
1
, i.e., the bit
1
.
Further, to read the written data from the bit
1
, voltages of 1.5V, 0V and 3V are applied to the bit line
2
, the bit line
1
and the word line, respectively. At this stage, a threshold voltage increases immediately below the bit
1
due to electrons injected in the bit
1
, which reduces a read current. Accordingly, data reading can be performed by detecting the reduction of the read current.
Data writing and reading for a bit
2
(b
2
) can be performed by switching the voltages applied to the bit lines
1
and
2
.
In a device wherein a minimum gate length is about 0.35 &mgr;m, the width of the charge accumulating region is as small as 100 Å or less, so that charges in one bit does not influences those in another bit.
On the other hand, data erasing is performed by injecting holes to the silicon nitride film
31
through the underlying silicon oxide film
32
. For example, to erase data from the bit
1
shown in FIGS.
17
(
a
) and
17
(
b
), voltages of 8V, 3V and 0V are applied to the bit line
1
, the bit line
2
and the word line, respectively. Accordingly, holes are generated by a tunneling phenomenon between bands, accelerated by a lateral electric field and injected to the silicon nitride film
31
through the lower silicon oxide film
32
. Thus, data in the bit
1
is erased.
In the above-mentioned NROM cell, the two bits (b
1
and b
2
) are controlled by one gate voltage (the word line). That is, the selected cell and a cell adjacent thereto are located between a source and a drain (between the bit lines) so that the same voltage is applied to the cells by one word line, which deteriorates reading precision. With the deteriorated reading precision, a margin for data reading is also reduced so that slight movement of electrons and holes causes erroneous reading. Thus, the device becomes less reliable.
Further, where an effective channel length is reduced in accordance with the progress of miniaturization of the semiconductor device, a distance between adjacent bits is reduced and lateral movement of electrons and holes tends to influence the device. That is, charges in one bit influence those in another bit. Accordingly, erroneous reading is caused, control of writing and erasing becomes difficult, the number of verification increases and an accurate voltage control is required. This results in a decrease of writing and erasing speeds.
Further, the data writing is carried out by hot electron injection so that writing is slow and power consumption is great.
SUMMARY OF THE INVENTION
In view of the above-described problems, the present invention has been achieved to provide a nonvolatile semiconductor memory device of improved reading precision wherein a plurality of bits formed between a pair of impurity diffusion layers are controlled by the same or different gate voltage(s) using gate electrodes each corresponding to the bits, a process of manufacturing the device and a method of operating the device.
According to the present invention, provided is a nonvolatile semiconductor memory device comprising: a pair of impurity diffusion layers formed on a surface of a semiconductor substrate;
two control gates formed on the semiconductor substrate through the intervention of a charge accumulating layer, the two control gates being provided between the pair of impurity diffusion layers and adjacent to each of the impurity diffusion layers;
a word gate transistor including a word line formed on the semiconductor substrate through the intervention of a word gate insulating film-between the control gates,
wherein the two control gates and the word gate transistor are connected in series to form a unit cell.
Further, according to the present invention, provided is a process of manufacturing a nonvolatile semiconductor memory device comprising the steps of: (a) forming at least two of device isolation films parallel to each other along the X-axis on a semiconductor substrate;
(b) depositing an ONO film, a polysilicon film for control gates and a silicon nitride film successively on the semiconductor substrate including the device isolation films and patterning them into a desired configuration to form at least two of control gates parallel to each other along the Y-axis;
(c) forming a plurality of impurity diffusion layers which are parallel to each other along the Y-axis and adjacent to the control gates;
(d) forming an oxide film on the impurity diffusion layers and between the control gates to bury the oxide film between the control gates;
(e) removing the oxide film buried between the control gates; and
(f) forming a word gate transistor between the control gates.
The present invention further provides a method of writing data in the above-described nonvolatile semiconductor memory device comprising:
applying a predetermined positive voltage to one of the impurity diffusion layers;
applying a voltage higher than the voltage applied to the impurity diffusion layer to one of the control gates adjacent to the impurity diffusion layer, or a voltage almost equal to the voltage applied to the impurity diffusion layer to one of the, control gates adjacent to the impurity diffusion layer;
applying a voltage higher than a threshold voltage of other control gate to the other control gate; and
applying a voltage almost equal to a threshold voltage of the word gate transistor to the word gate to write data in a bit corresponding to said one control gate.
The present invention further provides a method of erasing data from the above-described nonvolatile semiconductor memory device comprising: applying a predetermined negative voltage to one of the control gates, and
grounding the substrate or applying a predetermined positive voltage to the substrate or applying a predetermined positive voltage to an impurity diffusion layer adjacent to said one control gate to erase data from a bit corresponding to said one control gate.
The present invention further provides a method of reading data from the above-described nonvolatile semiconductor memory device comprising: applying a predetermined positive voltage to one of the impurity diffusion layers,
applyi
Sugita Yasuhiro
Yamauchi Yoshimitsu
Nguyen Dao H.
Nixon & Vanderhye P.C.
LandOfFree
Nonvolatile semiconductor memory device, process of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory device, process of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device, process of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3012176