Nonvolatile semiconductor memory device operable at high speed w

Details Nonvolatile semiconductor memory device operable at high speed w Nonvolatile semiconductor memory device operable at high speed w

1998-03-03

2000-08-22

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257320, 257326, 257378, 365177, H01L 29788

Patent

active

061076597

ABSTRACT:
A memory cell array of a nonvolatile semiconductor memory device is provided with a bipolar transistor whose base is connected to a node between sources of two memory cell transistors. A memory cell SL decoder controls the potential level of an emitter of the bipolar transistor. A collector of the bipolar transistor is held at a ground potential. In a read operation, the emitter potential is so controlled that the bipolar transistor enters an ON state, and a current flowing through a channel of either memory cell transistor is amplified by the bipolar transistor to be read.

REFERENCES:
patent: 5060194 (1991-10-01), Sakui et al.
patent: 5350938 (1994-09-01), Matsukawa et al.
patent: 5483483 (1996-01-01), Choi et al.
patent: 5659505 (1997-08-01), Kobayashi et al.
"A Novel NAND Structure with a BJT Contact for the High Density Mask ROMs", Choi, et al, 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 163-164.

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