Nonvolatile semiconductor memory device including pillars...

Details Nonvolatile semiconductor memory device including pillars... Nonvolatile semiconductor memory device including pillars...

2009-03-20

2011-12-27

Landau, Matthew (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S326000, C257S328000, C257SE27103

Reexamination Certificate

active

08084809

ABSTRACT:
In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

REFERENCES:
patent: 2007/0252201 (2007-11-01), Kito et al.
patent: 2007-266143 (2007-10-01), None
H. Tanaka, et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, Symposium on VLSI Technology Digest of Technical Papers, 2007, pp. 14-15.
Yoshiaki Fukuzumi, et al., “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory”, IEDM, 2007, pp. 449-452.

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