Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1989-11-22
1992-07-28
Gossage, Glenn
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, 36518905, 3652385, G11C 0000
Patent
active
051345838
ABSTRACT:
A semiconductor memory device has a plurality of memory blocks, each block including a matrix arrangement of a plurality of nonvolatile memory elements. The device is also provided with at least one redundant data line which is selectively employed in place of a defective data line associated with a defective address in a memory block. The data lines corresponding to the respective memory blocks are selectively coupled to corresponding ones of first common data lines by a Y selector circuit in accordance with outputs of a first Y decoder, while a redundant data line is controllably coupled to a redundant common data line by a redundant selector circuit in accordance with an output of a redundant decoder. A plurality of data latch circuits are provided for transmitting therethrough write information data in accordance with outputs of a second Y decoder and a second redundant decoder, each one of the plurality of data latch circuits being paired with a respective one of a plurality of write amplifiers which transmit the write signals to the common data lines and redundant common data line. Therefore, of the plurality of data lines being addressed in the plurality of memory blocks, only a defective data line which corresponds to a defective address is replaced with a respective redundant data line.
REFERENCES:
patent: 4599709 (1986-07-01), Clemons
patent: 4601019 (1986-07-01), Shah et al.
patent: 4788665 (1988-11-01), Fukuda
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 4910710 (1990-03-01), Kobatake
Matsuo Akinori
Nakamura Yasuhiro
Wada Masashi
Wada Takeshi
Watanabe Masashi
Gossage Glenn
Hitachi , Ltd.
Hitachi VLSI Engineering Corp.
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