Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2003-06-27
2004-05-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S065000, C365S072000, C365S149000, C365S214000, C365S230030, C365S230060
Reexamination Certificate
active
06735107
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and more particularly to a nonvolatile semiconductor memory device having ferroelectric capacitors.
Recently, semiconductor memories are widely used in various portions such as the main storages of large-scale computers, personal computers, domestic products, portable telephones and the like. As the types of semiconductor memories, a volatile DRAM (Dynamic RAM) and SRAM (Static RAM), nonvolatile MROM (Mask ROM) and flash E
2
PROM are on the market. Particularly, even though DRAM has a defect in which information cannot be maintained when the power supply is cut off since it is a volatile memory, it is excellent in its low cost (the cell area is ¼ times that of an SRAM) and high operation speed (in comparison with flash E
2
PROM) and DRAMs have a dominant share of the market. The flash E
2
PROM which is a rewritable nonvolatile memory can maintain information even if the power supply is cut off, but since it has a defect in which the number of rewriting operations (W/E number) is only approx. 10 to the sixth power, the write time is approx. some microseconds and an application of high voltage (12V to 22V) is required for data writing, flash E
2
PROMs do not dominate the market as much as DRAMs.
Since a nonvolatile memory (ferroelectric RAM) having ferroelectric capacitors has various advantages that it is nonvolatile, the number of rewriting operations is 10 to the twelfth power, the readout/write time is approximately equal to that of DRAM and the operation voltage is 3V to 5V, it may take the lion's share of the memory market and various makers have developed ferroelectric RAMs since they were proposed in 1980.
FIG. 1
shows a memory cell with the construction of one transistor and one capacitor in the conventional ferroelectric memory and a cell array construction. The construction of the memory cell MC in the conventional ferroelectric memory is obtained by connecting the current path of a cell transistor CT in series with a cell capacitor (ferroelectric capacitor) FC. A cell array CA includes bit lines BL, /BL for reading out data, word lines WL
0
, WL
1
for selecting the cell transistors CT, and plate lines PL
0
, PL
1
for driving one-side electrodes of the ferroelectric capacitors FC. A row decoder (more precisely, row decoder and plate driver) RD for driving the word lines WL
0
, WL
1
and plate lines PL
0
, PL
1
is arranged on one end of the cell array CA.
FIG. 2
shows an example of the structure of the memory cell MC. The ferroelectric capacitors FC includes a bottom electrode BE (plate electrode PL), ferroelectric material film FE and top electrode TE and the top electrode TE is connected to a metal interconnection M
1
via a contact TW. The metal interconnection M
1
is connected to an active area AA used as the drain of the cell transistor CT via a contact AW. Another active area AA used as the source of the cell transistor CT is connected to a metal interconnection M
1
via a contact AW and the metal interconnection M
1
is connected to a bit line /BL formed of a metal interconnection M
2
by a contact VIA.
With the cell array construction of FIG.
1
and the memory cell structure of
FIG. 2
, the following problem occurs. That is, since the word lines WL
0
, WL
1
are formed by extending the gate electrodes of the cell transistors CT, it is difficult to form gate interconnection layers with low resistance, and as a result, the sheet resistance thereof becomes several ohms/□ or more. Therefore, if an attempt is made to reduce the chip size by increasing the area of the memory cell array mat and lowering the ratio of the area of the row decoder RD, an amount of gate delay becomes excessively large. Likewise, since the plate lines PL
0
, PL
1
are formed of a material such as Pt, Ir, IrO
2
, Ru, StRuO, the sheet resistance thereof becomes several ohms/□ or more. Therefore, if an attempt is made to reduce the chip size by increasing the area of the memory cell array mat and lowering the ratio of the area of the row decoder RD, an amount of delay by the plate lines PL
0
, PL
1
becomes excessively large.
In order to solve the above problem, a word line shunt system used in the DRAM or the like or a hierarchical word line system shown in
FIG. 3
may be used.
FIG. 3
is a block diagram showing a cell array of a ferroelectric memory using the hierarchical word line system. The cell array CA is divided into a plurality of sub-cell arrays SCA and sub-row decoders (sub RD) SRD are respectively disposed for the sub-cell arrays SCA. A circuit for driving sub-word lines SWL
0
to SWL
3
used as the gates of the memory cell transistors in the sub-array SCA is arranged in the sub-row decoder SRD. On one-end side of the cell array CA, a main row decoder (main RD) MRD is disposed and main word lines MWL
0
, MWL
1
are formed to extend from the main row decoder MRD over the cell array CA and connected to each of the sub-row decoders SRD. The sub-row decoders SRD derive the logical product of signals supplied via the main word lines MWL
0
, MWL
1
and signals (word line driving signals) selectively supplied via word line driving signal lines MDV
0
to WDV
7
to generate driving signals SWL
0
to SWL
3
. For example, when the signal of the main word line MWL
0
is at the high level and the signal of the word line driving signal line MDV
0
is set at the high level, the signal of the sub-word line SWL
0
is set to the high level.
With the above construction, only a simple decode circuit and driver circuit are arranged in each of the sub-row decoders SRD and a decode circuit for selecting one of a plurality of main word lines MWLi (i=0, 1, . . . ) according to an external address can be commonly arranged in the main row decoder MRD. As a result, the number of row decoder circuits can be reduced in comparison with the cell array construction shown in
FIG. 1
, the area of the sub-row decoder SRD can be reduced and the chip size can be reduced while the operation speed is maintained. Likewise, the area of the sub-row decoder SRD in the plate line driving circuit can be reduced.
However, in the above system, as shown in the cross sectional view of the memory cell MC in
FIG. 4
, only a structure in which a metal interconnection M
3
is newly formed above the metal interconnection M
2
and the main word line MWL is formed to extend to various portions can be used, and as a result, an additional process step of forming the metal interconnection layer is necessary, which raises the production costs.
Thus, in the conventional ferroelectric memory, there occurs a problem that the chip area increases if the hierarchical word line system is not used and the process cost rises if the hierarchical word line system is used.
The inventor of the present application has proposed a new ferroelectric memory which is nonvolatile and simultaneously attains the three features of (1) small memory cells of 4F
2
size, (2) plane transistors which can be easily formed and (3) highly flexible random access function in Jpn. Pat. Appln. KOKAI Publication No. 10-255483 (U.S. Pat. Nos. 5,903,492 and 6,094,370 which were filed based on the prior application used as part of the basic application and are now pending) which is a prior application of the present application.
FIGS. 5A and 5B
show examples of the construction and operation of the ferroelectric memory relating to the prior application. In the prior application, each memory cell MC is constructed by connecting the current path of a cell transistor CT in parallel with a ferroelectric capacitor FC. One memory cell block MCB is constructed by serially connecting a plurality of parallel-connected memory cells MC, connecting one end thereof to a bit line /BL or BL via a block selection transistor BST and connecting the other end thereof to a plate line PL or /PL. The ON/OFF states of the cell transistors CT are controlled by selectively driving word lines WL
0
to WL
7
by outputs of a row decoder RD. The ON/OFF state of the block selection
Banner & Witcoff , Ltd.
Nelms David
Pham Ly Duy
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