Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-21
2004-12-28
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C258S005000, C258S005000
Reexamination Certificate
active
06835978
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-291910, filed Sep. 26, 2000, and No. 2001-272224, filed Sep. 7, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, particularly, to a gate structure of a semiconductor device having a nonvolatile memory transistor including a floating gate and a control gate, a selective transistor arranged close to said memory transistor, and a peripheral circuit mounted to the same chip.
2. Description of the Related Art
Known is a flash memory having a memory transistor including a floating gate and a control gate, a selective transistor arranged close to the memory transistor, and a peripheral circuit for driving the memory transistor and the selective transistor mounted to the same chip. A typical flash memory is called a NAND type flash memory. The NAND type flash memory includes a plurality of memory transistors connected in series, a selective transistor arranged close to the both edge portions of the memory transistor, and a peripheral circuit transistor for driving the memory transistor and the selective transistor. The region in which are arranged the memory transistors is called a memory cell array region, the region in which is arranged the selective transistor is called a selective gate region, and the region in which is arranged the peripheral circuit transistor is called a peripheral circuit region.
The method of preparing the flash memory of this type includes, for example, the steps of forming a gate insulating film on a semiconductor layer, depositing a polycrystalline silicon (polysilicon) film providing the floating gate of the memory transistor on the gate insulating film, and forming an element isolating region. In this case, a gate electrode of a two layer structure consisting of a floating gate and a control gate is present in at least a portion of the selective gate region and the peripheral circuit region as in the memory cell array region. It should be noted that it is necessary for the transistor in the selective gate region and the peripheral circuit region to be electrically connected to an upper wiring by withdrawing the floating gate. A conventional semiconductor device of this type will now be described.
FIG. 46A
is a plan view showing the memory cell array region and the selective gate region of the semiconductor device according to the first prior art.
FIG. 46B
is a plan view showing the peripheral circuit region of the semiconductor device according to the first prior art.
FIG. 47A
is cross sectional view of the semiconductor device along the line XXXXVIIA—XXXXVIIA shown in
FIGS. 46A and 46B
.
FIG. 47B
is cross sectional view of the semiconductor device along the line XXXXVIIB—XXXXVIIB shown in FIG.
46
A. The first a prior art is disclosed in Japanese Patent Disclosure (Kokai) No. 11-163304.
As shown in
FIGS. 46A
,
46
B,
47
A and
47
B, a first insulating film
12
is formed on a semiconductor layer
11
, and a first floating gate electrode layer
13
a
is formed on the first insulating film
12
. Then, an element isolating groove is formed and the element isolating groove thus formed is filled with an insulating film. The insulating film if planarized until the first floating gate electrode layer
13
a
is exposed to the outside so as to form an element isolating region
15
. Then, a second floating gate layer
13
b
consisting of polysilicon is formed on the first floating gate layer
13
a
and the element isolating region
15
, followed by patterning the second floating gate electrode layer
13
b
by a lithography and an etching. Consequently, an open potion
50
is formed on the element isolating region
15
of the memory sell array region and the open potion
50
isolated the second floating gate electrode layer
13
b
. Further, a second insulating film
16
is formed on the second floating gate electrode layer
13
b
and the element isolating region
15
, followed by forming a control gate electrode layer
18
on the second insulating film
16
. After the control gate electrode layer
18
, the second insulating film
16
and the first and second floating gate electrode layers
13
a
and
13
b
are patterned, a third insulating film
19
is formed on the entire surface of the semiconductor layer
11
. Further, after a contact hole is formed in the third insulating film
19
, a wiring
21
connected to the contact hole
20
is formed. As a result, the wiring
21
is connected to the control gate electrode layer
18
via the contact hole
20
in the memory cell array region, and the wiring
21
is connected to the first and second floating gate electrode layers
13
a
,
13
b
via the contact hole
20
in the selective gate region and the peripheral circuit region.
The semiconductor device according to the first prior art described above comprises a floating gate of the double layer structure consisting of the first and second floating gate electrode layers
13
a
and
13
b
. In the floating gate of the particular construction, the first floating gate electrode layer
13
a
is self-aligned with the element isolating region
15
, and the second floating gate electrode layer
13
b
is pulled up onto the element isolating region
15
. However, the first prior art described above gives rise to problems.
First of all, in the memory cell array region, it was necessary to set the width P of the open portion
50
such that the open portion
50
is not buried with the second insulating film
16
. It was also necessary to ensure an aligning allowance Q between the open portion
50
and the element region
10
in the lithography. However, it was difficult to finely adjust the open portion
50
because of the limit in the resolution of the photoresist in patterning the open portion
50
. As a result, it was difficult to achieve the fineness beyond a certain level, with the result that it was difficult to make the memory cell finer.
On the other hand, in the peripheral circuit region, the contact hole
20
is formed on the element isolating region
15
, making it possible to avoid the damage done to the element region. However, the element region is formed a long distance away from the connecting portion
25
between the second floating gate electrode layer
13
b
and the contact hole
20
. Therefore, since the second floating gate electrode layer
13
b
is formed of in general an electrode material having a high resistivity such as polysilicon, the delay caused by the resistance is increased so as to lower the performance of the element. It should also be noted that, if the second floating gate electrode layer
13
b
is allowed to extend over the element isolating region
15
, a capacitance coupling is formed between the semiconductor layer
11
and the floating gate with the insulating film of the element isolating region
15
interposed therebetween, leading to an increased RC delay.
Particularly, when it comes to the selective transistor of the NAND type flash memory, the increase in the RC delay described above is a serious problem to be solved. The contact to the second floating gate electrode layer
13
b
is formed as required for several cells within the memory cell array. The contact portion requires an area so as to increase the area of the memory cell array. Also, since the contact hole
20
can be formed in only a part of the memory cell array, the contact hole
20
is connected to the transistor via the second floating gate electrode layer
13
b
formed of polysilicon having a high resistivity. It follows that the problem of the RC delay time to the transistor positioned remote from the contact hole
20
is rendered serious. It should be noted that the increase in the delay time of the selective transistor adversely affects the reading speed of the memory cell.
FIG. 48A
is a plan view showi
Kamigaichi Takeshi
Matsui Michiharu
Mori Seiichi
Shirota Riichiro
Takeuchi Yuji
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Thien F
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