Nonvolatile semiconductor memory device having bitlines...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185020, C365S185170

Reexamination Certificate

active

07405978

ABSTRACT:
A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend from the cell array along a single direction. A common source line is formed in a common source layer and adapted to provide a predetermined source voltage to the plurality of memory cells. A voltage control block comprising a plurality of voltage control circuits adapted to control the voltage levels of the plurality of bitlines through voltage supply lines formed in a voltage-line metal layer is formed on one side of the cell array.

REFERENCES:
patent: 6927990 (2005-08-01), Mukai
patent: 7110292 (2006-09-01), Hahn et al.
patent: 2004/0057266 (2004-03-01), Mukai
patent: 2007/0053218 (2007-03-01), Hahn et al.
patent: 2004055617 (2004-02-01), None
patent: 2007-73962 (2007-03-01), None
patent: 100172443 (1998-10-01), None
patent: 100221024 (1999-06-01), None

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