Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-05-08
1997-02-04
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518527, 36518529, 36518909, G11C 700
Patent
active
056005920
ABSTRACT:
In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval with such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.
REFERENCES:
patent: 4618876 (1986-10-01), Stewart et al.
patent: 4642798 (1987-02-01), Rao
patent: 4879679 (1989-11-01), Kikuda et al.
patent: 4893257 (1990-01-01), Tanaka et al.
patent: 4902058 (1990-03-01), Sakai
patent: 5022000 (1991-06-01), Terasawa et al.
patent: 5043788 (1991-08-01), Omoto et al.
patent: 5047981 (1991-09-01), Gill et al.
patent: 5051953 (1991-09-01), Kitazawa et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5122985 (1992-06-01), Santin
patent: 5134449 (1992-07-01), Gill et al.
patent: 5157218 (1992-10-01), Santin et al.
patent: 5168335 (1992-12-01), D'Arrigo et al.
patent: 5223451 (1993-06-01), Uemura et al.
patent: 5243559 (1993-09-01), Murai
patent: 5295102 (1994-03-01), McClure
patent: 5295106 (1994-03-01), Jinbo
patent: 5297088 (1994-03-01), Yamaguchi
patent: 5374838 (1994-12-01), Sawada et al.
patent: 5396459 (1995-03-01), Arakawa
T. Nakayama, "A New Decoding Scheme and Erase Sequence for 5V Only Sector Erasable Flash Memory",1992 Symposium on VLSI Circuit, Jun. 4-6, 1992/Seattle, pp., 22 & 23.
A. Umezawa, "A 5-V --Only Operation 0.6-.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1540-1545.
Atsumi Shigeru
Tanaka Sumio
Kabushiki Kaisha Toshiba
Le Vu A.
Nelms David C.
LandOfFree
Nonvolatile semiconductor memory device having a word line to wh does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory device having a word line to wh, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device having a word line to wh will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-685881