Nonvolatile semiconductor memory device having a drain...

Details Nonvolatile semiconductor memory device having a drain... Nonvolatile semiconductor memory device having a drain...

1996-05-15

2001-10-09

Abraham, Fetsum (Department: 2508)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S317000, C257S336000, C257S344000, C257S497000, C257S321000, C257S322000, C438S231000, C438S232000, C438S305000, C438S306000

Reexamination Certificate

active

06300656

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and in particular to a so-called flash memory, i.e., an EEPROM (electrically Erasable and Programmable Read Only Memory) allowing electrical erasing and writing of information, and a method of manufacturing the same.
2. Description of the Background Art
EEPROMs have been known as a kind of nonvolatile semiconductor memory devices which allow free programming of data and also allow electrical writing and erasing of information. Although the EEPROM has an advantage that both writing and erasing can be executed electrically, it requires two transistors, i.e., a select transistor and a memory transistor for each memory cell, so that integration to a higher degree is difficult. In view of this, there has been proposed a flash EEPROM, in which each memory cell is formed of one transistor, and entire written information charges can be electrically erased at a time. This is disclosed, for example, in U.S. Pat. No. 4,868,619.
FIG. 81
is a block diagram showing a general structure of a flash memory. Referring to
FIG. 81
, the structure includes a memory cell matrix
100
, an X-address decoder
200
, a Y-gate
300
, a Y-address decoder
400
, an address buffer
500
, a write circuit
600
, a sense amplifier
700
, an I/O buffer
800
and a control logic
900
.
Memory cell matrix
100
includes a plurality of memory transistors arranged in a matrix form. Memory matrix
100
is connected to X-address decoder
200
and Y-gate
300
. X-address decoder
200
and Y-gate
300
function to select rows and columns in memory cell matrix
100
, respectively. Y-gate
300
is connected to Y-address decoder
400
. Y-address decoder
400
functions to provide information for selecting columns. X-address decoder
200
and Y-address decoder
400
are connected to address buffer
500
. Address buffer
500
functions to store temporarily address information.
Y-gate
300
is connected to write circuit
600
and sense amplifier
700
. Write circuit
600
functions to perform writing during data inputting. Sense amplifier
700
functions to determine “0” or “1” as a value of a current which flows during data outputting. Write circuit
600
and sense amplifier
700
each are connected to I/O buffer
800
. I/O buffer
800
functions to store temporarily input/output data.
Address buffer
500
and I/O buffer
800
are connected to control logic
900
. Control logic
900
functions to control the operation of flash memory. Control logic
900
performs control based on a chip enable signal /CE, an output enable signal /OE and a program signal. Characters “/” in reference characters such as “/CE” mean inversion.
FIG. 82
is an equivalent circuit diagram showing a schematic structure of memory cell matrix
100
shown in FIG.
81
. Referring to
FIG. 82
, memory cell matrix
100
is provided with a plurality of word lines WL
1
, WL
2
. . . , WL
i
and a plurality of bit lines BL
1
, BL
2
. . . , BL
j
which extends perpendicularly to each other to form a matrix. The plurality of word lines WL
1
WL
2
. . . , WL
i
are connected to X-address decoder
200
and are disposed in the row direction. The plurality of bit lines BL
1
BL
2
. . . , BL
j
are connected to Y-gate
300
and are disposed in the column direction.
Memory transistors Q
11
, Q
12
, . . . , Q
ij
are arranged at crossings of the word lines and bit lines, respectively. Each memory transistor has a drain connected to the corresponding bit line. A control gate of each memory transistor is connected to the corresponding word line. A source of each memory transistor is connected to the corresponding source line S
1
, S
2
. . . , S
i
. The sources of memory transistors belonging to the same row are mutually connected.
A structure of each memory transistor forming the conventional flash memory will now be described below.
FIG. 83
is a fragmentary plan showing a schematic structure of memory cell matrix
100
of the conventional flash memory.
FIG. 84
is a cross section taken along line D-D′ in FIG.
83
.
Referring mainly to
FIG. 84
, a p-type silicon substrate
1
is provided at its main surface with drain diffusion regions
13
and a source diffusion region
12
which are spaced from each other with channel regions
2
therebetween, respectively. A floating gate electrode
4
is formed on each channel region
2
with a thin oxide film
3
of about 100 Å in thickness therebetween. A control gate electrode
6
is formed on floating gate electrode
4
with an interlayer insulating film
5
therebetween. Floating gate electrode
4
and control gate electrode
6
are made of polycrystalline silicon doped with impurity, which will be referred to as “doped polycrystalline silicon” hereinafter. A thermal oxide film
51
is formed over p-type silicon substrate
1
, floating gate electrode
4
and control gate electrode
6
. A smooth coat film
8
made of, e.g., an oxide film is formed over floating gate electrode
4
and control gate electrode
6
.
Smooth coat film
8
is provided with a contact hole
9
reaching a portion of a surface of source diffusion region
12
. A bit line
52
, which has a portion electrically connected to source diffusion region
12
through contact hole
9
, extends on smooth coat film
8
.
Referring mainly to
FIG. 83
, the plurality of word lines
6
are arranged perpendicularly to the plurality of bit lines
52
. Each word line
6
is integral with the plurality of control gate electrodes
6
. At each of crossings of word lines
6
and bit lines
52
, there is formed floating gate electrode
4
located under control gate electrode
6
. There are also formed element isolating oxide films
53
, each of which is formed between two areas each including two floating gate electrodes
4
neighboring to each other in the column direction.
Referring to
FIG. 85
, description will be given on a write operation of a flash EEPROM utilizing channel hot electrons. A voltage V
D1
of about 6 to 8V is applied to drain diffusion region
13
, and a voltage V
G1
of about 10 to 15V is applied to control gate electrode
6
. Voltages V
D1
and V
G1
thus applied generate a large amount of high energy electrons near drain diffusion region
13
and oxide film
3
. The electrons thus generated are partially introduced into floating gate electrode
4
. Since the electrons are accumulated in floating gate electrode
4
in this manner, a threshold voltage V
TH
of the memory transistor increases. The state where threshold voltage V
TH
is higher than a predetermined value is a written state and is called a “0” state.
Referring to
FIG. 86
, an erase operation utilizing an F-N (Fowler-Nordheim) tunnel phenomenon will be described below. A voltage V
S
of about 10 to 12V is applied to source diffusion region
12
, control gate electrode
6
is set to the ground potential, and drain diffusion region
13
is held at the floating state. Voltage V
S
applied to source diffusion region
12
generates an electric field, which causes the F-N tunnel phenomenon to move electrons from floating gate electrode
4
through thin oxide film
3
. Since electrons are removed from floating gate electrode
4
, threshold voltage V
TH
of the memory transistor lowers. The state where threshold voltage V
TH
is lower than the predetermined value is an erased state and is called an “1” state.
In a read operation, a voltage V
G2
of about 5V is applied to control gate electrode
6
shown in
FIG. 84
, and a voltage V
D2
of about 1 to 2V is applied to drain diffusion region
13
. The foregoing determination of “1” or “0” is performed based on whether a current flows through the channel region of memory transistor, i.e., whether the memory transistor is on or off. Thereby, information is read.
For the flash memory described above, there has been proposed a drain structure (which will be referred to as a “pocket structure”) shown in
FIGS. 87 and 88
in order to improve write characteristics.
FIG. 88
sh

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