Nonvolatile semiconductor memory device and producing method...

Details Nonvolatile semiconductor memory device and producing method... Nonvolatile semiconductor memory device and producing method...

2009-08-12

2011-10-25

Tran, Tan N (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S002000, C257S390000

Reexamination Certificate

active

08044456

ABSTRACT:
A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

REFERENCES:
patent: 2006/0110877 (2006-05-01), Park et al.
patent: 2008/0012064 (2008-01-01), Park et al.
U.S. Appl. No. 13/033,026, filed Feb. 23, 2011, Nitta.
U.S. Appl. No. 13/044,973, filed Mar. 10, 2011, Nitta.
U.S. Appl. No. 12/886,090, filed Sep. 20, 2010, Minemura, et al.

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