Nonvolatile semiconductor memory device and method of...

Details Nonvolatile semiconductor memory device and method of... Nonvolatile semiconductor memory device and method of...

2006-12-07

2010-06-15

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S711000, C714S718000, C714S723000, C365S201000

Reexamination Certificate

active

07739560

ABSTRACT:
A test interface receives a test command designating execution of a test for a memory cell. The test storage circuit stores test information necessary to execute the test. The test storage circuit includes an erasable programmable storage unit. The decoder decodes the test command input to the test interface, and selects the test information stored in the test storage circuit. The sense amplifier reads out, from the test storage circuit, the test information selected by the decoder. The holding circuit holds the test information read out by the sense amplifier. The control circuit controls a test operation of checking whether the memory cell normally operates, on the basis of the test information held in the holding circuit. The defect storage circuit is formed for the memory cell, and stores fail information indicating that the memory cell is defective if the memory cell does not normally operate in the test operation.

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