Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-09
2001-12-11
Jackson, Jr., Jerome (Department: 2515)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S324000, C438S257000
Reexamination Certificate
active
06329688
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device and a method of manufacturing the same, and in particular relates to an EEPROM (Electrically Erasable and Programmable Read Only Memory) allowing electrical erasing and writing, and more particularly to a so-called flash memory as well as a method of manufacturing the same.
2. Description of the Background Art
An EEPROM, which allows free programming of data and also allows electrical writing and erasing of information, has been known as a kind of nonvolatile semiconductor memory device. The EEPROM has an advantage that both writing and erasing can be electrically performed, but has a disadvantage that high density integration is difficult because two transistors, i.e., a select transistor and a memory cell transistor are required in a memory cell. In view of this, a flash memory which requires one transistor for each memory cell and allows electrical erasing of entire written information charges at a time has been proposed.
FIG. 38
is a block diagram showing a general structure of a flash memory of a NOR type. Referring to
FIG. 38
, the flash memory includes a memory cell matrix
1100
, an X-address decoder
1200
, a Y-gate
1300
, a Y-address decoder
1400
, an address buffer
1500
, a write circuit
1600
, a sense amplifier
1700
, an I/O buffer
1800
and a control logic
1900
.
Memory cell matrix
1100
internally has a plurality of memory cell transistors arranged in rows and columns. Memory cell matrix
1100
is connected to X-address decoder
1200
and Y-decoder
1300
. X-address decoder
1200
and Y-gate
1300
are operable to select the row and column in memory cell matrix
1100
, respectively. Y-gate
1300
is connected to Y-address decoder
1400
. Y-address decoder
1400
is operable to provide apply information for selecting the column. X-address decoder
1200
and Y-address decoder
1400
are connected to address buffer
1500
. Address buffer
1500
is operable to store temporarily address information.
Y-gate
1300
is connected to write circuit
1600
and sense amplifier
1700
. Write circuit
1600
is operable to perform a write operation during input/output of data. Sense amplifier
1700
is operable to determine “0” and “1” from a value of current which flows during the data output. Write circuit
1600
and sense amplifier
1700
each are connected to an I/O buffer
1800
. I/O buffer
1800
is operable to store temporarily the input/output data.
Address buffer
1500
and I/O buffer
1800
are connected to a control logic
1900
. Control logic
1900
is operable to control an operation of the flash memory. Control logic
1900
performs control based on a chip enable signal /CE, an out-chip enable signal /OE and a program signal. The character “/” in the reference characters such as “/CE” means the inversion or inverted state.
FIG. 39
is an equivalent circuit diagram showing a schematic structure of memory cell matrix
1100
shown in FIG.
38
. Referring to
FIG. 39
, a plurality of word lines WL
1
, WL
2
, . . . WL
i
and a plurality of bit lines BL
1
, BL
2
, . . . BL
j
which extend perpendicularly to the word lines to form a matrix are arranged in memory cell matrix
1100
. The plurality of word lines WL
1
, WL
2
, . . . WL
i
are connected to X-address decoder
1200
and extend in the row direction. The plurality of bit lines BL
1
, BL
2
, . . . BL
j
are connected to Y-gate
1300
and extend in the column direction.
Memory transistors Q
11
, Q
12
, . . . Qij are arranged at crossings between the word lines and bit lines, respectively. A drain of each memory cell is connected to the corresponding bit line. A control gate of each memory transistor is connected to the corresponding word line. Sources of the memory transistors are connected to corresponding source lines S
1
, S
2
, . . . Si. The source lines of the memory transistors belonging to the same row are connected together.
A structure of the memory transistor forming the conventional flash memory will now be described below.
FIG. 40
is a fragmentary plan showing a schematic structure of memory matrix
1100
of the conventional NOR-type flash memory.
FIG. 41
is a cross section taken along line D-D′ in FIG.
40
.
Referring primarily to
FIG. 41
, a p-type silicon substrate
1001
has a main surface, on which drain diffusion regions
1013
and source diffusion regions
1012
spaced by a predetermined distance are formed to define channel regions
1002
therebetween. A floating gate electrode
1004
is formed on each channel region
1002
with a thin oxide film
1003
of about 100 Å in film thickness therebetween. A control gate electrode
1006
is formed on each floating gate electrode
1004
with an interlayer insulating film
1005
therebetween. Floating gate electrode
1004
and control gate electrode
1006
are made of polycrystalline silicon doped with impurity (which will be referred to as “doped polycrystalline silicon” hereinafter). p-type silicon substrate
1001
, floating gate electrodes
1004
and control gate electrodes
1006
are covered with a thermal oxide film
1051
. There is also formed a smooth coat film
1008
which is made of, e.g., an oxide film and covers floating gate electrodes
1004
and control gate electrodes
1006
.
Smooth coat film
1008
is provided with contact holes each reaching a portion of the surface of source diffusion region
1012
. Bit lines
1052
are formed over smooth coat film
1008
and are connected to source diffusion regions
1012
through contact holes
1009
, respectively.
Referring primarily to
FIG. 40
, the plurality of word lines
1006
and the plurality of bit lines
1052
are perpendicular to each other. Word line
1006
is formed integrally with control gate electrode
1006
. Floating gate electrode
1004
is formed at the crossing between word line
1006
and bit line
1052
, and more specifically is located under control gate electrode
1006
. Two floating gate electrodes
1004
which neighbor to each other in the column direction are covered by a common LOCOS (Local Oxidation of Silicon) film
1053
.
Referring to
FIG. 42
, description will be given on a write operation of the NOR-type flash memory utilizing channel hot electrons. A voltage V
D1
from about 4 to about 6 V is applied to drain diffusion region
1013
, and a voltage V
G1
from about 10 to about 15 V is applied to control gate electrode
1006
. Voltages V
D1
and V
G1
thus applied generate a large number of high energy electrons at the vicinities of drain diffusion region
1013
and oxide film
1003
. A part of the electrons are injected into floating gate electrode
1004
. When floating gate electrode
1004
accumulates the electrons in this manner, a threshold voltage V
TH
of the memory transistor increases. The state in which threshold voltage V
TH
exceeds a predetermined value is a written state and is called a state of “0”.
Referring to
FIG. 43
, description will be given on an erasing operation utilizing a F-N (Fowler-Nordheim) tunneling phenomenon. A voltage V
S
from about 10 to about 12 V is applied to source diffusion region
1012
, control gate electrode
1006
is set to a ground potential, and drain diffusion region
1013
is held at a floating state. Owing to an electric field formed by voltage V
S
applied to source diffusion region
1012
, the F-N tunneling phenomenon occurs, and thereby the electrons in floating gate electrode
1004
pass through thin oxide film
1003
. In this manner, the electrons are extracted from floating gate electrode
1004
, so that threshold voltage V
TH
of the memory transistor lowers. The state in which the threshold voltage is lower than the predetermined value is the erased state, and is also called a state of “1”.
In the read operation, as shown in
FIG. 41
, a voltage V
G2
of about 5 V is applied to control gate electrode
1006
, and a voltage V
D2
from about 1 to about 2 V is applied to drain diffusion region
1013
. In this case, the foregoing determinat
Eckert II George C.
Jackson, Jr. Jerome
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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