Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-13
2002-11-05
Wojchechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S321000, C257S322000, C438S621000, C438S630000
Reexamination Certificate
active
06476438
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and particularly relates to a structure of a nonvolatile semiconductor memory device, which can improve a coupling ratio between a floating gate electrode and a control gate electrode, as well as a method of manufacturing the same.
2. Description of the Background Art
A self-align STI (Shallow Trench Isolation) has been known as a technique for improving a density in a nonvolatile semiconductor memory device. The self-align STI is a technique for forming a trench in a self-aligned fashion using patterned doped polycrystalline silicon, which will form floating gate electrodes in a memory cell part.
FIG. 33
is a cross section of a conventional nonvolatile semiconductor memory device employing the self-align STI.
As shown in
FIG. 33
, the nonvolatile semiconductor memory device includes a peripheral circuit part and a memory cell part. A silicon oxide film
2
for element isolation is formed at a main surface of a semiconductor substrate
1
in the peripheral circuit part, and a trench
3
and a silicon oxide film
21
for element isolation are formed for at the main surface of semiconductor substrate
1
in the memory cell part.
Memory cell transistors are formed in the memory cell part. Each memory cell transistor has a floating gate electrode
8
formed on the main surface of semiconductor substrate
1
with a thermal oxide film
4
therebetween, an insulating film
9
and a control gate electrode
35
.
Floating gate electrode
8
is formed of a doped polycrystalline silicon film
6
, and control gate electrode
35
has a doped polycrystalline silicon film
10
and a WSi film
11
. A silicon oxide film
12
is formed on control gate electrode
35
.
MOS (Metal Oxide Semiconductor) transistors are formed in the peripheral circuit part. The MOS transistor has a gate electrode
13
formed on semiconductor substrate
1
with a thermal oxide film
5
therebetween. Gate electrode
13
has doped polycrystalline silicon film
10
and WSi film
11
. Silicon oxide film
12
is formed on gate electrode
13
.
The memory cell transistors and the MOS transistors described above are covered with an interlayer insulating film
14
. Interlayer insulating film
14
has contact holes
15
, in which tungsten plugs
16
are formed, respectively. An interconnection film
17
electrically connected to tungsten plug
16
is formed on interlayer insulating film
14
.
A method of manufacturing the nonvolatile semiconductor memory device having the above structure will now be described with reference to
FIGS. 34-38
.
As shown in
FIG. 34
, silicon oxide film
2
is formed at the peripheral circuit part, and thermal oxide film
4
is formed on the main surface of semiconductor substrate
1
. Doped polycrystalline silicon film
6
is formed on thermal oxide film
4
, and is patterned.
Semiconductor substrate
1
masked with doped polycrystalline silicon film
6
is etched to form trench
3
at the memory cell part in a self-aligned fashion. Trench
3
is filled with silicon oxide film
21
.
Then, insulating film
9
is deposited on doped polycrystalline silicon film
6
, and photoresist
36
of a predetermined configuration is formed on insulating film
9
. Etching is effected using photoresist
36
as a mask so that insulating film
9
, doped polycrystalline silicon film
6
and thermal oxide film
4
on the peripheral circuit part are removed.
Then, as shown in
FIG. 36
, thermal oxide film
5
is formed on the peripheral circuit part, and doped polycrystalline silicon film
10
, WSi film
11
and silicon oxide film
12
are deposited on thermal oxide film
5
. Photoresist
37
of a predetermined configuration is formed on silicon oxide film
12
, and silicon oxide film
12
masked with photoresist
37
is etched.
After removing photoresist
37
, WSi film
11
and doped polycrystalline silicon film
10
masked with silicon oxide film
12
are etched. Thereby, control gate electrode
35
in the memory cell part and gate electrode
13
of the MOS transistor in the peripheral circuit part are formed as shown in FIG.
37
.
Photoresist
38
covering the peripheral circuit part is formed, and etching is effected on insulating film
9
and doped polycrystalline silicon film
6
in the memory cell part using photoresist
38
as a mask. Thereby, floating gate electrode
8
is formed in the memory cell part.
Thereafter, interlayer insulating film
14
is deposited, and each contact hole
15
is formed in interlayer insulating film
14
. Tungsten plug
16
is formed in contact hole
15
, and interconnection film
17
is formed on interlayer insulating film
14
. Through the steps described above, the nonvolatile semiconductor memory device shown in
FIG. 33
is completed.
In the nonvolatile semiconductor memory device shown in
FIG. 33
, trench
3
for element isolation is formed by etching semiconductor substrate
1
, which is masked with doped polycrystalline silicon film
6
forming floating gate electrode
8
. Therefore, independent photolithography for forming trench
3
is not required, and therefore, it is not necessary to ensure, in the photolithography step, an overlapping margin and a margin required in view of variations in size. Therefore, the density in the nonvolatile semiconductor memory device can be improved.
However, due to the fact that the overlapping margin and the margin for variations in size are not required for the photolithography as described above, the surface area of floating gate electrode
8
decreases in the main surface direction of semiconductor substrate
1
as shown in FIG.
33
.
This reduces the capacitance between control gate electrode
35
and floating gate electrode
8
, and lowers the coupling ratio.
SUMMARY OF THE INVENTION
The invention has been made for overcoming the foregoing disadvantage, and it is an object of the invention to provide a nonvolatile semiconductor memory device, in which a coupling ratio between a control gate electrode and a floating gate electrode is improved.
A nonvolatile semiconductor memory device according to the invention includes a semiconductor substrate having a main surface; a floating gate electrode having a first conductive film formed on the main surface with a tunnel insulating film therebetween, and a second conductive film laid over the first conductive film and having a convexity; an insulating film covering the second conductive film; and a control gate electrode formed on the insulating film.
As described above, the second conductive film of the floating gate electrode is provided with the convexity, and the insulating film and the control gate electrode cover the convexity. Thereby, a capacitor can be formed between the convexity and the control gate electrode. This can increase the capacitance between the floating gate electrode and the control gate electrode.
Since the floating gate electrode has the multilayer structure formed of the conductive films, the following advantages can be achieved. The characteristics of the tunnel insulating film are significantly affected by a state of an interface between the semiconductor substrate and the tunnel insulating film as well as a state of an interface between the tunnel insulating film and the floating gate electrode. However, when forming the first conductive film, which will form the lower conductive film of the floating gate electrode, and thus when forming the interface between the tunnel insulating film and the floating gate electrode, an impurity concentration of the first conductive film, which is required for achieving a good state of the interface, may not match with an impurity concentration, which is electrically optimum for the floating gate electrode. Accordingly, the floating gate electrode is formed of, e.g., a multilayer structure having the first and second conductive films. Owing to this structure, the impurity concentration of the first conductive film can be kept at a value required for forming
Mitsubishi Denki & Kabushiki Kaisha
Wojchechowicz Edward
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