Nonvolatile semiconductor memory device and method for...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S244000, C257S314000, C257S261000, C257SE21209, C257SE29129, C257SE29300

Reexamination Certificate

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08035150

ABSTRACT:
A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.

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patent: 6703661 (2004-03-01), Wu
patent: 6716703 (2004-04-01), Hashimoto
patent: 7064375 (2006-06-01), Yonehama et al.
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patent: 2004/0079985 (2004-04-01), Yonehama et al.
patent: 2006/0001092 (2006-01-01), Kim
patent: 2006/0091447 (2006-05-01), Ema
patent: 2006/0170064 (2006-08-01), Yonehama et al.
patent: 2002-57230 (2002-02-01), None
patent: 2005-79282 (2005-03-01), None
U.S. Appl. No. 11/396,584, Keisuke Yonehama, et al.
Office Action issued Nov. 30, 2010, in Japanese Patent Application No. 2005-342289 (with English-language Translation).

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