Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-10-07
2004-12-07
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257S324000
Reexamination Certificate
active
06828621
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and to a method for fabricating the same. In particular, it relates to a nonvolatile semiconductor memory device having memory elements and peripheral circuits for inputting and outputting data to and from the memory elements formed on a single semiconductor substrate and to a method for fabricating the same.
At present, flash EEPROM (Electrically Erasable Programmable ROM) devices (hereinafter referred to as FEEPROM devices) have been used widely in electronic equipment as nonvolatile semiconductor memory devices which allow for electrical write and erase operations. The structures of memory cells in a nonvolatile semiconductor memory element can be divided roughly into two types, which are a stacked-gate type having a multilayer electrode structure composed of a floating gate electrode and a control gate electrode stacked on a semiconductor substrate and a split-gate type having an electrode structure composed of a floating gate electrode and a control gate electrode each opposed to a channel region in a semiconductor substrate.
The memory cells of the split-gate type are larger in size than those of the stacked-gate type because of the floating gate electrode and the control gate electrode disposed adjacent to each other on the semiconductor substrate. In addition, the floating gate electrode and the control gate electrode adjacent to each other are formed by individual lithographic steps, which requires a margin for the alignment of respective masks used to form the floating gate electrode and the control gate electrode. With the margin, the memory cells tend to be further increased in size.
FIGS. 58A
to
58
H show the cross-sectional structures of a conventional split-gate FEEPROM device in the individual process steps.
First, as shown in
FIG. 58A
, an insulating film
202
is formed on a semiconductor substrate
201
composed of silicon. Then, control gate electrodes
203
are formed selectively on the insulating film
202
.
Next, as shown in
FIG. 58B
, the portion of the insulating film
202
on the region of the semiconductor substrate
201
to be formed with drains is removed therefrom by wet etching by using a first mask pattern
251
having an opening corresponding to the drain formation region and the gate electrodes
203
as a mask. Then, boron (B) ions at a relatively low dose are implanted into the semiconductor substrate
201
such that a lightly doped p-type region
204
is formed in the drain formation region.
Next, as shown in
FIG. 58C
, a silicon dioxide film having a thickness of about 100 nm and doped with boron (B) and phosphorus (P) (BPSG (Boron Phosphorus Silicate Glass)) film is deposited over the entire surface of the semiconductor substrate
201
. The deposited BPSG film is etched back by anisotropic etching to form sidewalls
205
composed of the BPSG film on the both side surfaces of each of the control gate electrodes
203
.
Next, as shown in
FIG. 58D
, dry etching is performed with respect to the semiconductor substrate
201
by using a second mask pattern
252
having an opening corresponding to the drain formation region of the semiconductor substrate
201
, the gate electrode
203
, and the side walls
205
as a mask, thereby forming a recessed portion
201
a
having a stepped portion composed of the portion of the semiconductor substrate
201
underlying the sidewall
205
as the upper stage and the drain formation region as the lower stage.
Next, as shown in
FIG. 58E
, arsenic (As) ions at a relatively low dose are implanted into the semiconductor substrate
201
by using the second mask pattern
252
, the gate electrode
203
, and the sidewall
205
as a mask, whereby an LDD region
206
as a lightly doped n-type region is formed in the drain formation region.
Next, as shown in
FIG. 58F
, the sidewalls
205
are removed by using vapor-phase hydrofluoric acid and the semiconductor substrate
201
is thermally oxidized in an oxygen atmosphere at about 850° C., whereby a thermal oxide film
207
with a thickness of about 9 nm is formed over the entire surface of the semiconductor substrate
201
including the gate electrodes
203
. The portion of the thermal oxide film
207
overlying the drain formation region serves as a tunnel oxide film for each of floating gate electrodes.
Next, a polysilicon film doped with phosphorus (P) is deposited over the entire surface of the semiconductor substrate
201
and etched back to form sidewalls composed of the polysilicon film on the both side surfaces of the control gate electrodes
203
. Then, as shown in
FIG. 58G
, the sidewall closer to a region to be formed with sources is removed, while the sidewall closer to the drain formation region of the semiconductor substrate
201
is divided into parts corresponding to individual memory cells on a one-by-one basis, thereby forming floating gate electrodes
208
composed of the polysilicon film in the drain formation region.
Next, as shown in
FIG. 58H
, arsenic (As) ions are implanted into the semiconductor substrate
201
by using the gate electrodes
203
and the floating gate electrodes
208
as a mask such that source and drain regions
209
and
210
are formed in the source formation region and in the drain formation region, respectively, whereby memory cells in the FEEPROM device are completed.
Since the floating gate electrodes
208
each opposed to the control gate electrode
203
via the thermal oxide film
208
serving as a capacitance insulating film is thus formed by self alignment relative to the control gate electrode
203
, it is sufficient to perform only one lithographic step for forming the gate electrode
203
and a displacement does not occur between the control gate electrode
203
and the floating gate electrode
208
during the alignment thereof.
In a typical method for fabricating the conventional FEEPROM device, however, the floating gate electrode
208
, the thermal oxide film
207
, and the control gate electrode
203
covered with the thermal oxide film
207
which are shown in
FIG. 58G
are mostly composed of polysilicon, a silicon dioxide, and polysilicon, respectively. This causes the problem that, if the floating gate electrode
208
is to be formed selectively by etching, the control gate electrode
203
composed of the same material composing the floating gate electrode
208
may be damaged unless the etching speed is controlled with high precision.
Although the thermal oxide film
207
serving as the capacitance insulating film between the control gate electrode
203
and the floating gate electrode
208
and serving as the tunnel insulating film between the floating gate electrode
208
and the semiconductor substrate
201
is formed in the single step illustrated in
FIG. 58F
, if the tunnel film is formed after the formation of the capacitance insulating film, the interface between the control gate electrode
203
and the capacitance insulating film is oxidized or a bird's beak occurs at the interface, which causes the problem that the thickness of the capacitance insulating film is increased locally and the capacitance insulating film does not have a specified capacitance value.
In the split-gate or stacked-gate FEEPROM device, if not only the memory cells but also other elements, particularly active elements such as MOS transistors each of which controls carriers implanted from the source region by using the gate electrode, are formed on a single semiconductor substrate, it is typical to simultaneously form the control gate electrodes of the FEEPROM device and the gate electrodes of the MOS transistors.
In terms of reducing the number of fabrication process steps, the conventional fabrication method is desirable since it simultaneously forms the control gate electrodes of the memory cells and the gate electrodes of the MOS transistors contained in, e.g., peripheral circuits or the like for controlling the memory cells. However, the memory cells of a FEEPROM device are larger in element size than MOS
Fujimoto Hiromasa
Kamada Akihiro
Kusumi Masataka
Noro Fumihiko
Odanaka Shinji
Lewis Monica
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Wilczewski Mary
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