Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-14
2004-08-03
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S321000, C257S336000, C257S339000, C257S345000
Reexamination Certificate
active
06770931
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and to a method for fabricating the same. At present, flash EEPROM (Electrically Erasable Programmable ROM) devices are used widely in electronic equipment as nonvolatile semiconductor memory devices which allow for electrical write and erase operations. The structures of memory cells in the nonvolatile semiconductor memory devices can be divided broadly into two types. The first one is a stacked-gate type having a multilayer electrode structure composed of a floating gate electrode and a control gate electrode which are stacked successively on a semiconductor substrate. The second one is a split-gate type having an electrode structure composed of a floating gate electrode and a control gate electrode which are disposed adjacent to each other in opposing relation to a channel region in a semiconductor substrate.
Referring to the drawings, a description will be given herein below to a conventional split-gate nonvolatile semiconductor memory device.
FIG. 42
shows a cross-sectional structure of a split-gate nonvolatile semiconductor memory device disclosed in U.S. Pat. No. 5,780,341, which has a stepped portion formed in a portion of a semiconductor substrate underlying a floating gate electrode. As shown in
FIG. 42
, a main surface of a semiconductor substrate
201
composed of, e.g., p-type silicon is formed with a stepped portion
205
composed of a first surface region
202
serving as an upper stage, a second surface region
204
serving as a lower stage, and a step side region
204
connecting the upper and lower stages.
A control gate electrode
210
is formed on the first surface region
202
of the stepped portion
205
with a gate insulating film
211
interposed therebetween. A floating gate electrode
212
formed to cover up the stepped portion
205
is capacitively coupled to the side surface of the control gate electrode
210
closer to the stepped portion and opposed to the second surface region
203
with a silicon dioxide film
213
serving as a tunnel film interposed therebetween.
A heavily doped n-type source region
221
is formed in the first surface region
202
of the semiconductor substrate
201
, while a lightly doped n-type drain region
222
a
is formed in an area of the second surface region
203
underlying the floating gate electrode
212
and a heavily doped drain region
222
b
is formed externally of the lightly doped drain region
222
a.
In an area of the first surface region
202
underlying the floating gate electrode
212
, a p-type impurity region
223
containing a p-type impurity at a concentration higher than in the semiconductor substrate
201
is formed. In such a structure, the floating gate electrode
212
is positioned in the direction in which electrons that have been injected into the heavily source region
221
flow so that the efficiency with which channel electrons are injected is improved.
As a result of conducting various studies including simulation and the like, the present inventors have concluded that the conventional split-gate nonvolatile semiconductor memory device is unsatisfactory in terms of the effect of increasing the efficiency of electron injection which is exerted by the stepped portion
205
formed in the semiconductor substrate
201
.
When an electric field is applied during a write operation, a high electric field is hard to propagate upwardly from the lower corner of the stepped portion
205
in the source-side end portion of the lightly doped drain region
222
a
so that the localization of the electric field is likely to occur only in the vicinity of the lower corner of the stepped portion
205
. As a result, a region where the electric field is intensest deviates to a lower portion from the step side region
204
into which the channel electrons from the floating gate electrode
212
are intended to be actually injected. The channel electrons flow directly to the lightly doped drain region
222
a
through a region at a distance from the step side region
204
. This prevents the channel electrons from being injected into the floating gate electrode
212
with a sufficiently high efficiency.
During an erase operation, the electrons accumulated in the floating gate electrode
212
are extracted as a FN tunnel current to the heavily doped drain region
222
b
through a tunnel film composed of the portion of the silicon dioxide film
213
opposed to the floating gate electrode
212
. With the increasing miniaturization of the element, however, the area of the portion of the tunnel film which permits the passage of the electrons is reduced so that the erase operation becomes difficult.
For an easier erase operation, there is a method of enhancing the electric field applied to the tunnel film by increasing the drain voltage. In accordance with the method, however, holes having high energy (hot holes) generated in the heavily doped drain region
222
b
are generated simultaneously. The hot holes causes the problem that the reliability of the tunnel film is lowered or that the hot holes are captured in the tunnel film to degrade the characteristics of the element.
As the element is reduced in size, especially the gate length of the control gate electrode
210
is reduced, a short-channel effect, which is obscure in the conventional split-gate flash EEPROM device, is observed distinctly disadvantageously.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to ensure, by solving the foregoing conventional problems, an improved efficiency with which electrons are injected into a nonvolatile semiconductor memory device having a stepped portion and allow a low-voltage and high-speed write operation.
A second object of the present invention is to increase an erase speed, while suppressing the occurrence of hot holes during an erase operation. A third object of the present invention is to allow miniaturization of an element by suppressing a short-channel effect.
To attain the first object, the present invention provides a nonvolatile semiconductor memory device having a stepped portion on the drain side, wherein a heavily doped impurity region of the conductivity type opposite to that of the drain region is formed at a position at a distance from and opposed to the upper corner of the stepped portion so as not to reach a first surface region and a step side region or adopts a method in which a proper substrate voltage is applied during a write operation.
To attain the second object, the present invention forms a drain region in which an impurity concentration is progressively higher with distance from a source region. To attain the third object, the present invention provides an impurity region of the conductivity type opposite to that of the source region such that the source region is covered with the impurity region.
Specifically, a first nonvolatile semiconductor memory device according to the present invention attains the first object and comprises: a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the first surface region; a control gate electrode formed on an area of the first surface region located in the vicinity of the stepped portion with the first insulating film interposed therebetween; a floating gate electrode formed on the semiconductor substrate so as to cover up the stepped portion, the floating gate electrode being capacitively coupled to a side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween and opposed to the second surface region with a third insulating film interposed therebetween; a source region formed in an area of the first surface region opposite to the floating gate electrode relative to the control gate electrode; a drain region formed in an area of th
Fujimoto Hiromasa
Odanaka Shinji
Ogura Seiki
Sugiyama Nobuyo
Jackson Jerome
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Nguyen Joseph
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