Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-08-01
2004-04-20
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S185090, C365S189090
Reexamination Certificate
active
06724671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for testing the same, and more particularly to a nonvolatile semiconductor memory device like an erasable and programmable read-only memory (referred to as ‘EPROM’ hereinafter), the information written to which can be erased by irradiation of ultraviolet rays, or an electrically erasable and programmable read-only memory (referred to as ‘EEPROM’ hereinafter), the information written to which can be electrically erased, and to a method for testing the EPROM or EEPROM.
2. Related Art
In the nonvolatile semiconductor memory device of the type as described above, there are used a lot of memory elements arranged as a matrix, of which each is provided with a floating gate and a control gate as well. The memory elements of this kind vary their threshold values depending on the presence or not of the electric charge injected into their floating gate.
For instance, in the memory element of the n-channel conductive type, the threshold value of the memory element can be made higher by injecting an electron into its floating gate, comparing with that of the memory element to which no electron injection is done. Accordingly, the information respectively stored in the electron injected memory element and the no electron injected memory element can be made out based on the difference between threshold values of these memory elements. For instance, when applying a predetermined gate voltage to the above-mentioned control gate, the data ‘0’ can be read out from the electron injected memory element while the data ‘1’ can be read out from the no electron injected memory element.
However, it would not be always guaranteed that the electric charge once injected into the floating gate of the memory element stably rests therein and the data ‘1’ or ‘0’ never fails to be read out correctly as described above. It might happen that the electric charge injected into the floating gate of the memory element is unexpectedly discharged for some unknown reason. In this case, the whole data are obliged to be rewritten. In order to prevent such an unexpected situation as described above, all the nonvolatile semiconductor memory devices newly coming from the production line are tested to examine if the electric charge injected into the floating gate is discharged or not under the predetermined load condition.
In order to carry out the prior art test of this kind, the electric charge is first injected in advance into the floating gate of all the memory elements. Then, a predetermined voltages are applied respectively to the source, drain and control gate of each electric charge injected memory element, for instance, 4.5V being applied to the drain by making use of the regulator incorporated into the nonvolatile semiconductor memory device, 3V to the source by making use of the write voltage for data latch, and 0V to the control gate.
If the electric charge once injected into the floating gate of the memory element is discharged by applying the above-mentioned voltages to the source, drain and control gate of the memory element, the memory element is judged to be a faulty product, and the nonvolatile semiconductor memory device including this faulty memory element is also judged to be a faulty product and is sorted out from normal products.
As described above, in the prior art test method, only a voltage lower than that of the drain was applied to the source of each memory element by making use of the write voltage from the data latch, so that this test method has not always satisfied the demand for the more severe and reliable test for sorting the faulty product. Accordingly, it has been desired to test the memory element under such a severer condition that the higher load is applied thereto, for instance.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a sorting test method capable of much more severely sorting out the faulty memory element than the prior art test method. Another object of the invention is to provide a nonvolatile semiconductor memory device capable of being tested by means of the more severer sorting test method than the prior art one.
In order to achieve the objects as described above, the invention adopts the following constitution.
Basically, the invention is characterized in that, in the test for judging whether or not a memory elements storing a binary information corresponding to the presence or not of an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated therefrom, said semiconductor substrate including a source and a drain formed thereon, can exactly hold the electric charge injected to the floating gate in advance, an approximately equal voltage is applied to the source and drain as the voltage for drawing out the electric charge held in the floating gate.
According to the invention, an approximately equal voltage is applied to the source and drain as a voltage for drawing out the electric charge injected into the floating gate in advance.
Furthermore, the nonvolatile semiconductor memory device according to the invention includes a power source unit, which makes it easier to carry out the test method according to the invention.
REFERENCES:
patent: 5838626 (1998-11-01), Nakayama
Hoang Huan
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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