Static information storage and retrieval – Read/write circuit – Erase
Patent
1993-01-15
1994-08-30
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Erase
265185, 265201, 265900, G11C 1606
Patent
active
053434340
ABSTRACT:
In a memory device in a bare chip state which is determined as fail by over erasing during a test at a wafer level, information indicating the presence of an over-erased memory cell is stored in a nonvolatile and readable manner into an identification memory circuit, and then memory cells in a memory cell array are restored to an erase state of an electrically neutral state by irradiation with an energy beam such as ultraviolet rays. A chip erased by the energy beam such as ultraviolet rays is assembled as an OTPROM (one-time programmable read only memory) and tested. At that time, a writing/erasing control circuit for controlling data writing into and data erasing in the memory cells is brought into an operation inhibited state in accordance with the information stored in the memory circuit. It is possible to reduce the rate at which fail products are produced by use of a flash memory which is determined as fail because of the presence of an over-erased memory cell as a one-time programmable memory device.
REFERENCES:
patent: 5237535 (1993-08-01), Mielke et al.
Mitsubishi Denki & Kabushiki Kaisha
Popek Joseph A.
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