Nonvolatile semiconductor memory device and electronic...

Details Nonvolatile semiconductor memory device and electronic... Nonvolatile semiconductor memory device and electronic...

2002-05-22

2003-09-16

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185010, C365S200000, C365S185200

Reexamination Certificate

active

06621734

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which allows redundant substitution information (e.g., address information), information used for device adjustments and the like to be written separately in a nonvolatile memory cell. The present invention also relates to an electronic information apparatus using such a nonvolatile semiconductor memory device.
2. Description of the Related Art
A conventional nonvolatile semiconductor memory device has a redundant function of substituting a malfunctioned word line, a malfunctioned bit line and a malfunctioned memory cell with a spare redundant word line, a spare redundant bit line and a spare redundant memory cell, respectively, so as to improve a defect rate.
In general, when the malfunctioned word line, bit line or memory cell is detected in a semiconductor memory device by a tester during a production shipment test, the tester causes a redundant address memory circuit provided in the same semiconductor memory device to store address information of the malfunctioned word line, line or memory cell. This address information stored in the redundant address memory circuit is ref erred to as the “malfunctioned address”, “redundant address” or “defective address”.
In a DRAM, an SRAM or the like, a redundant address memory circuit including fuses made of polysilicon is generally used while the nonvolatile semiconductor memory device, which uses floating gate transistors as memory cells of a main memory circuit, uses similar floating gate transistors to those of the main memory circuit as the memory cells of the redundant address memory circuit (hereinafter, referred to as the “redundant memory circuit”).
An operation principle of the conventional redundant memory circuit used in a nonvolatile semiconductor memory device is now described with respect to a case where a word line of the nonvolatile semiconductor memory device is defective. When the defective word line is substituted with the redundant word line, an address of the defective word line is stored in the redundant memory recruit
The redundant memory circuit is a memory circuit addressable according to contents (which is referred to as a “CAM (Content-Addressable Memory)”). When address information is input to the main memory circuit, this address information is always input to the redundant memory circuit (CAM) as well. When an address contained in the input information is identical to an address stored in the redundant memory circuit, the redundant memory circuit is validated so as to break the connection to the defective word line and switch over to the connection to the redundant word line.
In the main memory circuit having a capacity of about several mega bits, several defects can occur, and therefore the number of restorable defective word lines corresponds to the number of the redundant word lines provided in the main memory circuit. Each redundant word line is combined with a redundant memory circuit which stores address information for a corresponding defective word line. In order to correct for N defects, N redundant word lines and N redundant memory circuits are required. Further, the redundant memory circuit requires a single validation bit, which indicates that a redundant circuit corresponding to the redundant memory circuit can be actually operated when address information for the defective word line is input to the redundant memory circuit. Where word line address information for the main memory circuit has a size of M bits, the redundant memory circuit is required to include memory cells for at least M+1 bits of information. Accordingly, in order to satisfy these requirements, the total number of bits required by the redundant memory circuit is N×(M+1).
FIG. 5
shows one possible way of configuring memory and readout cells for a defective address bit (or a validation bit), that is, one of the M+1 cell circuits of the redundant memory circuit, and its associated redundant information readout circuit, is shown.
In
FIG. 5
, drains of floating gate transistors TGF
1
and TGF
2
are respectively connected to both ends (points C or D) of a latch circuit via respective NMOS transistors T
3
and T
4
, which are turned on during a reading operation. Sources of floating gate transistors TGF
1
and TGF
2
can be connected to ground (not shown). A source voltage VS applied to the floating gate transistors TGF
1
and TGF
2
is 0 V during reading or writing operations and is about 6 V during an erasing operation.
The NMOS transistors T
3
and T
4
also have a bias effect for reducing a drain voltage applied to the floating gate transistors TGF
1
and TGF
2
so as to prevent drain disturb caused to the floating gate transistors TGF
1
and TGF
2
. These two floating gate transistors TGF
1
and TGF
2
have a common word line VGF.
Sources of NMOS transistors T
9
and T
10
of this latch circuit are connected to a drain of an NMOS transistor T
8
which is turned off when the transistors TGF
1
and TGF
2
are in a reading operation. That is, during the reading operation, the latch circuit does not perform data-hold, and after the reading operation, i.e., after data has been validated, the latch circuit holds data. One end (point D) of the latch circuit is connected to a drain of an NMOS transistor T
7
for initializing data in the latch circuit. A source of the NMOS transistor T
7
is connected to ground.
NMOS transistors T
5
and TI
5
are connected in series between the drain of the floating gate transistor TGF
1
and a VPRG input port to which a write voltage VPRG is applied when writing data to the floating gate transistor TGF
1
. The NMOS transistors T
5
and TI
5
are always in an OFF state unless a writing operation is performed. Similarly, NMOS transistors T
6
and TI
6
are connected in series between the drain of the floating gate transistor TGF
2
and the VPRG input port.
When either one of the floating gate transistors TGF
1
and TGF
2
is programmed, an output Out of this cell circuit takes a logic level “0” or “1” according to a state of either one of the floating gate transistors TGF
1
and TGF
2
. An operation principle of reading data from the redundant memory circuit CAM is now described with respect to a case where the floating gate transistors TGF
1
and TGF
2
are respectively in an erasing state and a writing state.
Unlike a writing operation, in the operation of reading redundant information, all the transistors T
5
, TI
5
, T
6
and TI
6
are in an “OFF” state. Further, a read signal VB is at a low level and the transistors T
3
and T
4
are in an “OFF” state. In this case, the floating gate transistor TGF
1
is isolated from the PMOS transistor T
1
and the NMOS transistor T
9
of the latch circuit by the transistor T
3
, and the floating gate transistor TGF
2
is isolated from the PMOS transistor T
2
and the NMOS transistor T
10
of the latch circuit by the transistor T
4
.
Further, an inverted signal NVB to the readout signal VB is at a high level and the NMOS transistor T
8
is in an “ON” state. Accordingly, the latch circuit is formed by the transistors T
1
, T
2
, T
8
, T
9
and T
10
so as to hold data.
Thereafter, when an initialization signal INT is at a high level, the transistor T
7
is turned on so that a potential at point D (the drain side) of the transistor T
7
is at a low level (a ground level). The output Out provided via inverters INV
1
and INV
2
by the redundant memory circuit CAM has a low level equal to the level of the potential at point D.
On the other hand, at another output side (i.e., point C) of the latch circuit formed by the transistors T
1
, T
2
, T
8
, T
9
and T
10
, a voltage applied at point C is at a high level equal to the level of a power supply voltage Vcc since the transistor T
1
is turned on by the low-level potential at point D. Thereafter, when the initialization signal INT is at a low level, the transistor T
7
is turned off. Further, the readout signal VB is at a high level, and therefore the inverted sign

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